MPC8280 datasheet(948/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

30-10

Freescale Semiconductor

30.6

FCC Buffer Descriptors

Data associated with each FCC is stored in buffers. Each buffer is referenced by a buffer descriptor (BD).

All of the transmit BDs for an FCC are grouped into a TxBD circular table with a programmable length.

Likewise, receive BDs form an RxBD table. The user can program the start address of the BD tables

anywhere in system memory. See Figure 30-6.

Figure 30-6. FCC Memory Structure

The format of transmit and receive BDs, shown in Figure 30-7, is the same for every FCC mode of

operation except ATM mode; see Section 31.10.5, “ATM Controller Buffer Descriptors (BDs).” The first

16 bits in each BD contain status and control information, which differs for each protocol. The second 16

bits indicate the data buffer length in bytes (the wrap bit is the BD table length indicator). The remaining

32-bits contain the 32-bit address pointer to the actual buffer in memory.

Table 30-4. FTODR Field Descriptions

Field

Name

Description

TOD

Transmit on demand

0 Normal polling.

1 The CP gives high priority to the current TxBD and begins sending the frame does without waiting

for the normal polling time to check TxBD[R]. TOD is cleared automatically.

1–15

—

Reserved, should be cleared.

Rx Buffer

Status and Control

Data Length

Buffer Pointer

FCCx RxBD

Table

FCCx TxBD

Table

System Memory

Status and Control

Data Length

Buffer Pointer

Tx Buffer

Dual-Port RAM

Rx Buffer Descriptors

Tx Buffer Descriptors

FCCx RxBD

Table Pointer

(RBASE)

FCCx TxBD

Table Pointer

(TBASE)

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