MPC8280 datasheet(950/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

30-12

Freescale Semiconductor

30.7

FCC Parameter RAM

Each FCC parameter RAM area begins at the same offset from each FCC base area. The protocol-specific

portions of the FCC parameter RAM are discussed in the specific protocol descriptions. Table 30-5. shows

portions common to all FCC protocols.

Some parameter RAM values must be initialized before the FCC is enabled; other values are

initialized/written by the CP. Once initialized, most parameter RAM values do not need to be accessed by

user software because most activity centers around the TxBDs and RxBDs rather than the parameter RAM.

However, if the parameter RAM is accessed, note the following:

•

Parameter RAM can be read at any time.

•

Tx parameter RAM can be written only when the transmitter is disabled—after a STOP TRANSMIT

command and before a RESTART TRANSMIT command or after the buffer/frame finishes

transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT

command.

•

Rx parameter RAM can be written only when the receiver is disabled. Note the CLOSE RXBD

command does not stop reception, but it does allow the user to extract data from a partially full Rx

buffer.

•

See Section 30.12, “Disabling the FCCs On-the-Fly.”

Some parameters in Table 30-5. are not described and are listed only to provide information for

experienced users and for debugging. The user need not access these parameters in normal operation.

Table 30-5. FCC Parameter RAM Common to All Protocols Except ATM

Offset1

Name

Width

Description

0x00

RIPTR

Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for

data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless

it is stated otherwise in the protocol specification.

0x02

TIPTR

Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for

data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless

it is stated otherwise in the protocol specification. .

0x04

—

Hword Reserved, should be cleared.

0x06

MRBLR

Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that

the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver

can write fewer bytes to the buffer than MRBLR if a condition such as an error or

end-of-frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied

buffers should be at least as large as the MRBLR.

Note that FCC transmit buffers can have varying lengths by programming TxBD[Data

Length], as needed, and are not affected by the value in MRBLR.

MRBLR is not intended to be changed dynamically while an FCC is operating. Change

MRBLR only when the FCC receiver is disabled.

0x08

RSTATE

Word

Receive internal state. The high byte, RSTATE[0–7], contains the function code register;

see Section 30.7.1, “FCC Function Code Registers (FCRx).” RSTATE[8–31] is used by

the CP and must be cleared initially.

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