MPC8280 datasheet(939/1386 Pages) FREESCALE

939 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

30-1

Chapter 30

Fast Communications Controllers (FCCs)

The MPC8280’s three fast communications controllers (FCCs) are serial communications controllers

(SCCs) optimized for synchronous high-rate protocols. FCC key features include the following:

•

Supports HDLC/SDLC and totally transparent protocols

•

FCC clocks can be derived from a baud-rate generator or an external signal

•

Supports RTS, CTS, and CD modem control signals

•

Use of bursts to improve bus usage

•

Multibuffer data structure for receive and transmit, external buffer descriptors (BDs) anywhere in

system memory

•

192-byte FIFO buffers

•

Full-duplex operation

•

Fully transparent option for one half of an FCC (receiver/transmitter) while HDLC/SDLC protocol

executes on the other half (transmitter/receiver)

•

Echo and local loopback modes for testing

•

Assuming a 100-MHz CPM clock, the FCCs support the following:

– Full 10/100-Mbps Ethernet/IEEE 802.3x through an MII and RMII interface

– Full 155-Mbps ATM segmentation and reassembly (SAR) through UTOPIA (on FCC1 and

FCC2 only) (not available on the MPC8270)

– ATM internal rate mode for 31 PHYs

– ATM 31 PHY addresses for both FCC1 and FCC2

– 45-Mbps (DS-3/E3 rates) HDLC and/or transparent data rates supported on each FCC

FCCs differ from SCCs as follows:

•

No DPLL support.

•

No BISYNC, UART, or AppleTalk/LocalTalk support.

•

No HDLC bus.

•

Ethernet support only through an MII.

30.1

Overview

MPC8280 FCCs can be configured independently to implement different protocols. Together, they can be

used to implement bridging functions, routers, and gateways, and to interface with a wide variety of

standard WANs, LANs, and proprietary networks. FCCs have many physical interface options such as

interfacing to TDM buses, ISDN buses, standard modem interfaces, fast Ethernet interface (MII), and

ATM interfaces (UTOPIA); see Chapter 15, “Serial Interface with Time-Slot Assigner,” Chapter 36, “Fast

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