MPC8280 datasheet(937/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-47

29.10.1 Stopping and Restarting a Single-Channel

The following sequence must be followed to stop a single channel in order to change the MCC parameters

of the respective channel:

1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC

Commands,” or change the associated SI RAM entry to point to a channel which is not active and

wait for two frame periods in order to clear the internal FIFOs.

2. Change the channel parameters.

3. Enable the MCC channel(s) as described in Section 29.3.1.1, “Internal Transmitter State

(TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC

Mode,” or change the associated SI RAM entry to point to the respective channel.

The following sequence must be followed to stop a single channel in order to change the SI without using

the shadow SI:

1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC

Commands.”

2. Change the SI.

3. Enable the MCC channel as described in Section 29.3.1.1, “Internal Transmitter State

(TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC

Mode.”

It is possible to change the SI using the SI shadow while the channel is active. Both the primary and the

shadow configuration of the SI RAM must observe the configuration defined in MCCF (see Section 29.6,

“MCC Configuration Registers (MCCFx)”). The MCCF cannot be changed while there are active

channels.

29.10.2 Stopping and Restarting a Superchannel

The following sequence must be followed to stop a super channel in order to change the SI:

1. Issue a STOP command for the respective channel as described in Section 29.7, “MCC

Commands.”

2. Disable the TDM.

3. Change the SI.

4. Enable the TDM.

5. If necessary, change the MCC parameters (in DPRAM and external memory).

6. Enable the MCC channel(s) as described in Section 29.3.1.1, “Internal Transmitter State

(TSTATE)—HDLC Mode,” and Section 29.3.1.4, “Internal Receiver State (RSTATE)—HDLC

Mode.”

Under the following restrictions, the SI can be changed using the SI shadow while the channel is active:

•

Both the primary and the shadow configuration of the SI RAM must observe the configuration of

the super channel. Note that the super-channel table and MCCF register cannot be changed

dynamically.

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