MPC8280 datasheet(933/1386 Pages) FREESCALE

933 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-43

The data length and buffer pointer are described as follows:

•

Data length. Data length is the number of octets written by the CP into this BD’s data buffer. It is

written by the CP when the BD is closed. When this is the last BD in the frame (L = 1), the data

Continuous mode

0 Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed).

1 The empty bit (bit 0) is not cleared by the CP after this BD is closed, allowing the associated data

buffer to be overwritten automatically when the CP next accesses this BD. However, if an error

occurs during reception, the empty bit is cleared regardless of the CM bit setting.

—

Reserved, should be cleared.

User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this

bit is used.

—

Reserved, should be cleared.

Rx frame length violation (HDLC mode only). Indicates that a frame length greater than the

maximum value was received in this channel. Only the maximum-allowed number of bytes, MFLR

rounded to the nearest higher word alignment, are written to the data buffer. This event is recognized

as soon as the MFLR value is exceeded when data is word-aligned. When data is not word-aligned,

this interrupt occurs when the SDMA writes 64 bits to memory. The worst-case latency from MFLR

violation until detected is 7 bytes timing for this channel. When MFLR violation is detected, the

receiver is still receiving even though the data is discarded. The buffer is closed upon detecting a

flag, and this is considered to be the closing flag for this buffer. At this point, LG is set (1) and an

interrupt may be generated. The length field for this buffer is everything between the opening flag

and this last identifying flag.

Rx nonoctet-aligned frame. A frame of bits not divisible exactly by eight was received. NO = 1 for

any type of nonalignment regardless of frame length. The shortest frame that can be detected is of

type FLAG-BIT-FLAG, which causes the buffer to be closed with NO error indicated.

The following shows how the nonoctet alignment is reported and where data can be found.

To accommodate the extra word of data that may be written at the end of the frame, it is

recommended to reserve MFLR + 8 bytes for each buffer data.

Rx abort sequence. A minimum of seven consecutive 1s was received during frame reception. Abort

is not detected between frames. The sequence

Closing-Flag, data, CRC, AB, data, opening-flag...

does not cause an abort error. If the abort is long enough to be an idle, an idle line interrupt may be

generated. An abort within the frame is not reported by a unique interrupt but rather with a RXF

interrupt and the user has to examine the BD.

Rx CRC error. This frame contains a CRC error. The received CRC bytes are always written to the

receive buffer.

—

Reserved, should be cleared.

SS7 mode only: Short frame indication. Set if the received frame is less than 5 octets.

—

Reserved, should be cleared.

Table 29-21. RxBD Field Descriptions (continued)

Bits

Name

Description

msb

lsb

000...... 0

Valid data

Invalid data

xxx .................................... xx

MPC8280 Datasheet(PDF) 933 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 933 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL