MPC8280 datasheet(932/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-42

Freescale Semiconductor

29.9.1

Receive Buffer Descriptor (RxBD)

Figure 29-21 shows the RxBD.

RxBD fields are described in Table 29-21.

Offset + 0

—

LGNOABCR

SF1

1 SS7 mode only. Otherwise, reserved.

—

Offset + 2

Data Length

Offset + 4

Rx Data Buffer Pointer

Offset + 6

Figure 29-21. MCC Receive Buffer Descriptor (RxBD)

Table 29-21. RxBD Field Descriptions

Bits

Name

Description

Empty

0 The data buffer associated with this BD has been filled with received data, or data reception has

been aborted due to an error condition. The user is free to examine or write to any fields of this

RxBD. The CP does not use this BD again while the empty bit remains zero.

1 The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its

associated receive buffer are in use by the CP. When E = 1, the user should not write any fields

of this RxBD.

—

Reserved, should be cleared.

Wrap (final BD in table)

0 This is not the last BD in the RxBD table.

1 This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming

data into the first BD in the table (the BD pointed to by RBASE). The number of RxBDs in this

table is programmable and is determined by the wrap bit.

Interrupt

0 The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected.

1 The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been

used by the HDLC controller. These two bits may cause interrupts (if enabled).

Last in frame (only for HDLC mode of operation). The HDLC controller sets L = 1, when this buffer

is the last in a frame. This implies the reception either of a closing flag or of an error, in which case

one or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame

octets to the data length field.

0 This buffer is not the last in a frame.

1 This buffer is the last in a frame.

First in frame. The HDLC controller sets F = 1 for the first buffer in a frame. In transparent mode, F

indicates that there was a synchronization before receiving data in this BD.

0 This is not the first buffer in a frame.

1 This is the first buffer in a frame.

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