MPC8280 datasheet(935/1386 Pages) FREESCALE

935 / 1386 page

Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-45

The data length and buffer pointer are described below:

•

Data length. The data length is the number of bytes the MCC should transmit from this BD’s data

buffer. It is never modified by the CP. The value of this field should be greater than zero.

•

Tx buffer pointer. The transmit buffer pointer, which contains the address of the associated data

buffer, may be even or odd provided that SS7_OPT[SEN_FIS] = 0 (refer to Section 29.3.4.3, “SS7

Configuration Register—SS7 Mode”). If the automatic FISU option is required, the buffer pointer

must be 4-byte aligned. The buffer must reside in external memory. This value is never modified

by the CP.

Last

0 This is not the last buffer in the frame.

1 This is the last buffer in the current frame.

Tx CRC. Valid only when L = 1. Otherwise it is ignored.

0 Transmit the closing flag after the last data byte. This setting can be used for testing purposes to

send an erroneous CRC after the data.

1 Transmit the CRC sequence after the last data byte.

Continuous mode

0 Normal operation.

1 The CP does not clear the ready bit after this BD is closed, allowing the associated data buffer to

be retransmitted automatically when the CP next accesses this BD. However, the R bit is cleared

if an error occurs during transmission, regardless of the CM bit setting.

—

Reserved, should be cleared.

User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this

bit is used.

9–10

—

Reserved, should be cleared.

—

Reserved, should be cleared.

SUD

SS7 mode only: Signal unit delay

0 This buffer does not have a transmission delay.

1 A time delay of JTTDelay x 512 µs passes before this buffer is transmitted. Can be used for LSSU

transmission according to the JT Q.703 Standard which defines a 24 ms delay between

back-to-back LSSUs. This bit is only valid when SS7_OPT[STD] is set.

12–15

PAD

Pad characters. These four bits indicate the number of PAD characters (0x7E or 0xFF depending on

the IDLM mode selected in the CHAMR register) that the transmitter sends after the closing flag.

The transmitter issues a TXB interrupt only after sending the programmed number of pads to the Tx

FIFO buffer. The user can use the PAD value to guarantee that the TXB interrupt occurs after the

closing flag has been sent out on the TXD line. PAD = 0, means that the TXB interrupt is issued

immediately after the closing flag is sent to the Tx FIFO buffer. The number of PAD characters

depends on the FIFO size assigned to the channel in the MCC hardware. If the channel is not part

of a super channel then the MCC hardware assigns to this channel a fifo of 4 bytes. So in this case

a pad of 4 bytes ensures that the TXB interrupt is not given before the closing flag has been

transmitted over the TXD line. For a super channel, the FIFO length equals the number of time slots

assigned to the super channel multiplied by two.

Table 29-22. TxBD Field Descriptions (continued)

Bits

Name

Description

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