MPC8280 datasheet(964/1386 Pages) FREESCALE

964 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-4

Freescale Semiconductor

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Available bit rate (ABR)

— Performs ATMF UNI 4.0 ABR flow control on a per-VC basis

— Automatic forward-RM, backward-RM cells generation

— Automatic feedback rate adaptation

— Support for EFCI (explicit forward congestion indication) and ER (explicit rate)

— RM cell floating-point calculations

— Fully managed by CP with no host intervention

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Receive address look-up mechanism

— Two modes of address look-up are supported

– External CAM

– Address compression

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OAM (operations and maintenance) cells

— OAM filtering according to PTI field and reserved VCI field

— Raw cell queues for transmission and reception

— CRC-10 generation/check

— Performance monitoring support

– Support up to 64 bidirectional block tests simultaneously

– Automatic FMC and BRC cell generation and termination

– User transmit cell0+1 count

– User transmit cell0 count

– PM cells time stamp insertion

– Block error detection code (BEDC0+1) generation/check

– Total receive cell0+1 count

– Total receive cell0 count

— Specifying channel code for F5 OAM cells

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ATM layer statistic gathering on a per PHY basis.

— UTOPIA receiver error cells count (Rx parity error or short/long cells error)

— Misinserted cell count

— CRC-10 error cells count (ABR flow only)

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Memory management

— RxBD table per VC with option of global free buffer pool for AAL5

— TxBD table per VC

MPC8280 Datasheet(PDF) 964 Page - Freescale Semiconductor, Inc