MPC8280 datasheet(965/1386 Pages) FREESCALE

965 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-5

31.2

ATM Controller Overview

The following sections provide an overview of the transmitter and receiver portions of the ATM controller.

31.2.1

Transmitter Overview

Before the transmitter is enabled, the host must initialize the MPC8280 and create the transmit data

structure, described in Section 31.10, “ATM Memory Structure.” When data is ready for transmission, the

host arranges the BD table and writes the pointer of the first BD in the transmit connection table (TCT).

The host issues an ATM TRANSMIT command, which inserts the current channel to the ATM pace control

(APC) unit. The APC unit controls the ATM traffic of the transmitter. It reads the traffic parameters of each

channel and divides the total bandwidth among them. The APC unit can pace the peak cell rate,

peak-and-sustain cell rate (GCRA traffic) or peak-and-minimum cell rate traffic. The APC implements up

to eight priority levels for servicing real-time channels before non-real-time channels.

The transmitter ATM cell is 53–65 bytes and includes 4 bytes of ATM cell header, a 1-byte HEC, and 48

bytes of payload. The HEC is a constant taken from FDSRx[0–15] when using UTOPIA 16 and from

FDSRx[8–15] when using UTOPIA 8; see Section 30.4, “FCC Data Synchronization Registers (FDSRx).”

User-defined cells (UDC mode) include an extra header of 1–12 bytes with an optional HEC octet. Cell

transfers use the UTOPIA level II, cell-level handshake.

Transmission starts when the APC schedules a channel. According to the channel code, the ATM controller

reads the channel’s entry in the TCT and opens the first BD for transmission. In auto-VC-off mode, the

APC automatically deactivates the current channel when no buffer is ready to transmit. In this case, a new

ATM TRANSMIT

command is needed for transmission of the VC to resume.

31.2.1.1

AAL5 Transmitter Overview

The transmitter reads 48 bytes from the external buffer, adds the cell header, and sends the cell through the

UTOPIA interface. The transmitter adds any padding needed and appends the AAL5 trailer in the last cell

of the AAL5 frame. The trailer consists of CPCS-UU+CPI, data length, and CRC-32 as defined in ITU

I.363. The CPCS-UU+CPI (2-byte entry) can be specified by the user or optionally cleared by the

transmitter; see Section 31.10.2.3, “Transmit Connection Table (TCT).” The transmitter identifies the last

cell of the AAL5 message by setting the last (L) indication bit in the PTI field of the cell header. An

interrupt may be generated to indicate the end of the frame.

When the transmission of the current frame ends and no additional valid buffers are in the BD table, the

transmit process ends. The transmitter keeps polling the BD table every time this channel is scheduled to

transmit. Note that a buffer-not-ready indication during frame transmission aborts the frame transfer.

31.2.1.2

AAL1 Transmitter Overview

The MPC8280 supports both structured and unstructured AAL1 formats. For the unstructured format, the

transmitter reads 47 bytes from the external buffer and inserts them into the AAL1 user data field. The

AAL1 PDU header, which consists of the sequence number (SN) and the sequence number protection

(SNP) (CRC-3 and parity bit), is generated and inserted into the cell. The MPC8280 supports synchronous

residual time stamp (SRTS) generation using external PLL. If this mode is enabled, the MPC8280 reads

MPC8280 Datasheet(PDF) 965 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 965 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL