MPC8280 datasheet(966/1386 Pages) FREESCALE

966 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-6

Freescale Semiconductor

the SRTS code from the external logic and inserts it into four outgoing cells. See Section 31.16, “SRTS

Generation and Clock Recovery Using External Logic.”

For the structured format, the transmitter reads 47 or 46 bytes from the external buffer and inserts them

into the AAL1 user data field. The CP generates the AAL1 PDU header and inserts it into the cell. The

header consists of the SN, SNP, and the structured pointer.

The MPC8280 supports partially filled cells configured on a per-VC basis. In this mode (TCT[PFM] = 1),

only valid octets are copied from the buffer to the ATM cell; the rest of the cell is filled with padding octets.

31.2.1.2.1

AAL1 CES Transmitter Overview

Refer to Section 32.2, “AAL1 CES Transmitter Overview.”

31.2.1.3

AAL0 Transmitter Overview

No specific adaptation layer is provided for AAL0. The ATM controller reads a whole cell from an external

buffer, which always contains exactly one AAL0 cell. The ATM controller optionally generates CRC10

on the cell payload and places it at the end of the payload (CRC10 field). AAL0 mode can be used to send

OAM cells or AAL3/4 raw cells.

31.2.1.4

AAL2 Transmitter Overview

Refer to Section 33.3.1, “Transmitter Overview.”

31.2.1.5

Transmit External Rate and Internal Rate Modes

The ATM controller supports the following two rate modes:

•

External rate mode—The total transmission rate is determined by the PHY transmission rate. The

FCC sends cells to keep the PHY FIFOs full; the FCC inserts idle/unassign cells to maintain the

transmission rate.

•

Internal rate mode—The total transmission rate is determined by the FCC internal rate timers. In

this mode, the FCC does not insert idle/unassign cells. The internal rate mechanism supports up to

4 different rates. Each PHY has its own FTIRR, described in Section 31.15.1.1, “FCC Transmit

Internal Rate Register (FTIRRx).” The FTIRR includes the initial value of the internal rate timer.

A cell transmit request is sent when an internal rate timer expires. When using internal rate mode,

the user assigns one of the baud-rate generators (BRGs) to clock the four internal rate timers.

31.2.2

Receiver Overview

Before the receiver is enabled, the host must initialize the MPC8280 and create the receive data structure

described in Section 31.10, “ATM Memory Structure.” The host arranges a BD table for each ATM

channel. Buffers for each connection can be statically allocated (that is, each BD in the BD table is

associated with a fixed buffer location) or in the case of AAL5, can be fetched by the CP from a global

free buffer pool. See Section 31.10.5, “ATM Controller Buffer Descriptors (BDs).”

MPC8280 Datasheet(PDF) 966 Page - Freescale Semiconductor, Inc

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