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MPC8280 Datasheet(PDF) 998 Page - Freescale Semiconductor, Inc |
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MPC8280 Datasheet(HTML) 998 Page - Freescale Semiconductor, Inc |
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998 / 1386 page  ATM Controller and AAL0, AAL1, and AAL5 MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 31-38 Freescale Semiconductor 0x7C VCT1_BASE Word Base address of the address compression VC1 table. User-defined. 0x80 VP_MASK Hword VP mask for address compression lookup. User-defined. 0x82 VCIF Hword VCI filtering enable bits. When cells with VCI = 3, 4, 6, 7-15 are received and the associated VCIF bit = 1 the cell is sent to the raw cell queue. VCIF[0–2, 5] should be zero. See Section 31.10.1.2, “VCI Filtering (VCIF).” 0x84 GMODE Hword Global mode. User-defined. See Section 31.10.1.3, “Global Mode Entry (GMODE).” 0x86 COMM_INFO Hword The information field associated with the last host command. User-defined. See Section 31.14, “ATM Transmit Command.” 0x88 Hword 0x8A Hword 0x8C — Word Reserved, should be cleared. 0x90 CRC32_PRES Word Preset for CRC32. Initialize to 0xFFFF_FFFF. 0x94 CRC32_MASK Word Constant mask for CRC32. Initialize to 0xDEBB_20E3. 0x98 AAL1_SNPT_BASE Hword AAL1 SNP protection look-up table base address. (AAL1 CES only.) The 32-byte table resides in dual-port RAM. AAL1_SNPT_BASE must be halfword-aligned. User-defined offset from dual-port RAM base. See Section 31.10.6, “AAL1 Sequence Number (SN) Protection Table.” 0x9A — Hword Reserved, should be cleared. 0x9C SRTS_BASE Word External SRTS logic base address. AAL1 CES only. Should be 16-byte aligned. The four least-significant bits are taken from SRTS_DEV in the AAL1-specific area of the connection table entries. 0xA0 IDLE/UNASSIGN_BASE Hword Idle/unassign cell base address. Points to dual-port RAM area contains idle/unassign cell template (little-endian format). Should be 64-byte aligned. User-defined offset from dual-port RAM base. The ATM header should be 0x0000_0000 or 0x0100_0000 (CLP=1). 0xA2 IDLE/UNASSIGN_SIZE Hword Idle/unassign cell size. 52 in regular mode; 53–64 in UDC mode. 0xA4 EPAYLOAD Word Reserved payload. Initialize to 0x6A6A_6A6A. 0xA8 Trm Word (ABR only) The upper bound on the time between F-RM cells for an active source. TM 4.0 defines the Trm period as 100 msec. The Trm value is defined by the system clock and the time stamp timer prescaler; see Section 14.3.8, “RISC Time-Stamp Control Register (RTSCR).” For time stamp prescalar of 1µs, program Trm to be 100 ms/1µs = 100,000. 0xAC Nrm Hword (ABR only) Controls the maximum cells the source may send for each F-RM cell. Set to 32 cells. 0xAE Mrm Hword (ABR only) Controls the bandwidth between F-RM, B-RM and user data cell. Set to 2 cells. Table 31-11. ATM Parameter RAM Map (continued) Offset1 Name Width Description |
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