MPC8280 datasheet(1017/1386 Pages) FREESCALE

1017 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-57

31.10.2.3.7

UBR+ Protocol-Specific TCTE

Figure 31-35 shows the UBR+ protocol-specific TCTE.

Table 31-26 describes UBR+ protocol-specific TCTE fields.

31.10.2.3.8

ABR Protocol-Specific TCTE

Figure 31-36 shows the ABR protocol-specific TCTE.

Offset + 0x00

MCR

Offset + 0x02

—

MCR Fraction (MCRF)

Offset + 0x04

Maximum Delay Allowed (MDA)

Offset + 0x06–0x1E

—

Figure 31-35. UBR+ Protocol-Specific TCTE

Table 31-26. UBR+ Protocol-Specific TCTE Field Descriptions

Offset

Bits

Name

Description

0x00

—

MCR

Minimum cell rate for this channel. MCR is in units of APC time slots.

0x02

0–7

—

Reserved, should be cleared.

8–15

MCRF

Minimum cell rate fraction. Holds the minimum cell rate fraction of this channel in units of 1/256 slot.

0x04

—

MDA

Maximum delay allowed. The maximum time-slot service delay allowed for this priority level before

the APC reduces the scheduling rate from PCR to MCR.

0x06–

0x1E

—

Reserved, should be cleared.

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