MPC8280 datasheet(1020/1386 Pages) FREESCALE

1020 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-60

Freescale Semiconductor

31.10.3 OAM Performance Monitoring Tables

The OAM performance monitoring tables include performance monitoring block test parameters, as

shown in Figure 31-37. Each block test needs a 32-byte performance monitoring table in the dual-port

RAM. In the connection’s RCT and TCT, the user allocates an OAM performance table to a VCC or VPC.

See Section 31.6.6, “Performance Monitoring.” PMT_BASE in the parameter RAM points to the base

address of the tables. The starting address of each PM table is given by PMT_BASE + RCT/TCT[PMT]

× 32.

0x1C

—

Explicit rate. Holds the explicit rate value (in cells/sec) of the current ABR channel. ER is

copied to the F-RM cell ER field. The user usually initializes this field to PCR. ER uses the

ATMF TM 4.0 floating-point format.

0x1E

—

ER-BRM Explicit rate-backward RM cell. Holds the maximum explicit rate value (in cells/sec) allowed

for B-RM cells. The ER-TA field which is inserted to each B-RM cell is limited by this value.

ER-BRM uses the ATMF TM 4.0 floating-point format.

Offset + 0x00

FMCE TSTE

—

BLCKSIZE

Offset + 0x02

—

TX Cell Count (TCC)

Offset + 0x04

TUC1

Offset + 0x06

TUC0

Offset + 0x08

BEDC0+1-Tx

Offset + 0x0A

BEDC0+1-RX

Offset + 0x0C

TRCC1

Offset + 0x0E

TRCC0

Offset + 0x10

—

SN-FMC

Offset + 0x12

—

Offset + 0x14

PM CELL HEADER (VPI,VCI,PTI,CLP)

Offset + 0x16

Offset + 0x18

—

Offset + 0x1A

Offset + 0x1C

Offset + 0x1E

Figure 31-37. OAM Performance Monitoring Table

Table 31-27. ABR-Specific TCTE Field Descriptions (continued)

Offset

Bits

Name

Description

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