MPC8280 datasheet(1022/1386 Pages) FREESCALE

1022 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

31-62

Freescale Semiconductor

Figure 31-38. ATM Pace Control Data Structure

31.10.4.1 APC Parameter Tables

Each PHY’s APC parameter table, shown in Table 31-29, holds parameters that define the priority table

location, the number of priority levels, and other APC parameters. The table resides in the dual-port RAM.

The parameter APCP_BASE, described in Section 31.10.1, “Parameter RAM,” points to the base address

of PHY#0’s parameter table.

For multiple PHYs, the table structure is duplicated. Each table resides in 32 bytes of memory. The starting

address of each APC parameter table is given by APCP_BASE + PHY#

× 32. Note however that in slave

mode with multiple PHYs, the parameter table always resides at APCP_BASE regardless of the PHY

address.

Table 31-29. APC Parameter Table

Offset1

Name

Width

Description

0x00

APCL_FIRST

Hword Address of first entry in the priority table. Must be 8-byte aligned.

User-initialized.

0x02

APCL_LAST

Hword Address of last entry in the priority table. Must be 8-byte aligned. User-initialized

as APCL_FIRST + 8 x (number_of_priorities - 1).

0x04

APCL_PTR

Hword Address of current priority entry used by the CP. User-initialized with

APCL_FIRST.

0x06

CPS

Byte

Cells per slot. Determines the number of cells sent per APC slot. See

Section 31.3.2, “APC Unit Scheduling Mechanism.” User-defined. (0x01 = 1 cell;

0xFF = 255 cells.)

Note: If ABR is used, CPS must be a power of two.

0x07

CPS_CNT

Byte

Cells sent per APC slot counter. User-initialized to CPS; used by the CP.

0x08

MAX_ITERATION

Byte

Max iteration allowed. Number of scan iterations allowed in the APC.

User-defined. This parameter limits the time spent in a single APC routine,

thereby avoiding excessive APC latency.

Priority 1

APC Priority Table

APC Parameter Tables

Parameter Table

PHY #0

Parameter Table

PHY #1

Parameter Table

PHY #31

Priority 2

Priority 3

Priority 4

Priority 5

Priority 6

Priority 7

Priority 8

APC Scheduling Tables

Priority 1 Scheduling Table

Priority 2 Scheduling Table

Priority 3 Scheduling Table

Priority 4 Scheduling Table

Priority 5 Scheduling Table

Priority 6 Scheduling Table

Priority 7 Scheduling Table

Priority 8 Scheduling Table

Note: The shaded areas represent the active structures for an example implementation of PHY #0 with two

priorities. (The unshaded areas and dashed arrows represent unused structures.)

MPC8280 Datasheet(PDF) 1022 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1022 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL