MPC8280 datasheet(1075/1386 Pages) FREESCALE

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ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

32-15

the external framer. Each byte in the CAS block contains one nibble of valid CAS information (depicted

in Figure 32-8).

Note that the buffer data size should not include the CAS octets.

32.4.7.3.1

CAS Updates Using the Core (Optional)

To avoid using another TDM dedicated to CAS information, the user can use a parallel interface controlled

by the core to deliver the outgoing CAS block to the framer. In this case, the ATM receiver should be

programmed to operate in core CAS modify mode RCT[CCASM=1] (and RCT[CASM=1]). In this mode,

the CP adds an entry to the ATM interrupt queue and sets the appropriate sticky bit in OCASSR each time

an AAL1 cell is received with new signaling information (one or more signaling nibble has changed). (See

Section 32.10, “Outgoing CAS Status Register (OCASSR).”) A core interrupt service routine can then

write the updated outgoing CAS block to the framer.

Note to avoid additional latency, the interrupt queue assigned to this connection should have a global

interrupt threshold of one. See the INT_ICNT parameter discussed in Section 31.11.3, “Interrupt Queue

Parameter Tables.”

32.5

ATM-to-TDM Adaptive Slip Control

Two types of slip can occur in ATM-to-TDM operation: overrun and underrun. The two cases are handled

by the MCC and ATM controller automatically without requiring CPU intervention.

Overrun occurs when the MCC transmitter fetches data from the common BD table at a slower rate than

it is being filled by the ATM receiver. In this case, the ATM write pointer meets the MCC read pointer and

a BSY state is declared (an entry is added to the ATM interrupt table) on the ATM side.

Underrun occurs when the MCC transmitter fetches data from the common BD table at a higher rate than

it is being filled by the ATM receiver. In this case, the MCC read pointer reaches a BD that is not ready

and a buffer-not-ready state is declared on the MCC side.

In both slip cases, the MCC and ATM controller automatically recover and restart the ATM-to-TDM

interworking function.

In order to prevent overrun and underrun conditions, the MPC8280 maintains an adaptive slip control

using a set of 4 threshold pointers for each ATM-TDM (VC - super channel) connection.

The pre-underrun state (shown in Figure 32-14) occurs when the MCC read pointer goes faster than the

ATM write pointer. When the adaptive counter reaches the MCC_Stop threshold, the MCC read pointer

does not advance. At this point, the current BD (or the underrun template) is retransmitted a multiple of

the frame size. In the meantime, the ATM receiver continues to receive valid data and advance the ATM

write pointer. When the adaptive counter reaches the MCC_start threshold and the MCC has finished

sending a multiple of the frame size, the MCC starts to transmit the valid received data and advance the

MCC read pointer.

Note that when the pre-underrun state occurs, the MCC transmitter can transmit the last buffer

continuously or the underrun template. This is determined by the MCC channel configuration; see the

CHAMR[UTM] bit description in Section 29.3.2.3, “Channel Mode Register (CHAMR)—Transparent

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