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MPC8280 Datasheet(PDF) 1190 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1190 Page - Freescale Semiconductor, Inc

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Inverse Multiplexing for ATM (IMA)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
34-44
Freescale Semiconductor
34.4.6.1
Transmit Queues
Transmit queues are allocated on a per-link basis. They are circular queues of 64-byte buffers, defined by
their start and end pointers. For the transmit queue of the timing reference link (TRL), the queue must
consist of a minimum of four buffers (although it may consist of five buffers, if consistency of data
structures is desired). For the transmit queues of non-TRL links, the queues must consist of five buffers.
Queue fill and extract pointers must be initialized by software to the start of the queue; thereafter, these
pointers are managed by the microcode. The queue pointers must be on a 64-byte aligned boundary.
Figure 34-26. IMA Transmit Queue
34.4.6.2
Delay Compensation Buffers (DCB)
Cells received on a link are initially stored in a delay compensation buffer (DCB). DCBs are allocated on
a per-link basis. They are of user-definable length, thereby providing a programmable maximum
synchronizable delay. Note that DCBs of links within a group must all have the same size.
DCBs consist of a circular queue of 64-byte cell buffers. These cell buffers contain the received cell
followed by 12 bytes of header/status information.
Figure 34-27. Cell Buffer in Delay Compensation Buffer
The length of a DCB is defined by the link’s DCBSP and DCBEP parameters. The length of the DCB
(defined by (DCBEP-DCBSP) x 16) must be an integer multiple of the IMA frame length in bytes, M x 64.
Furthermore, the DCBSP must be aligned on a M x 64-byte boundary. For example, if M = 64, then DCBSP
must be on a 4KB boundary. To ensure group delay synchronization, the minimum length of the DCB
should be 2(Mx64).
IMA External Structure Region
Transmit
IMAEXTBASE
Queue
ITQSP
bits 0-11
bits 12-27
0000
bits 28-31
IMAEXTBASE
ITQEP
0000
IMAEXTBASE
64-byte boundary
ITQSP + TQ_SIZE - 4
64 bytes
12 bytes HEADER/STATUS
52 bytes RX CELL



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