MPC8280 datasheet(1269/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

37-7

Table 37-5 describes HDLC reception errors, which are reported through the RxBD.

Table 37-5. HDLC Reception Errors

Error

Description

Overrun Error

The HDLC controller maintains an internal FIFO buffer for receiving data. The CP begins

programming the SDMA channel and updating the CRC whenever data is received in the FIFO

buffer. When a receive FIFO overrun occurs, the channel writes the received data byte to the internal

FIFO buffer over the previously received byte. The previous byte and the frame status are lost. The

channel closes the buffer with RxBD[OV] set and generates the RXF interrupt if it is enabled. The

receiver then enters hunt mode. Even if the overrun occurs during a frame whose address is not

matched in the address recognition logic, an RxBD with data length two is opened to report the

overrun and the RXF interrupt is generated if it is enabled.

CD Lost During

Frame

Reception

When this error occurs, the channel terminates frame reception, closes the buffer, sets RxBD[CD],

and generates the RXF interrupt if it is enabled. This error has highest priority. The rest of the frame

is lost and other errors are not checked in that frame. At this point, the receiver enters hunt mode. If

CD is Lost during the first 8 serial bits it will not be reported as CD Lost error and there will be no

indication of error.

Abort Sequence The HDLC controller detects an abort sequence when seven or more consecutive ones are

received. When this error occurs and the HDLC controller receives a frame, the channel closes the

buffer by setting RxBD[AB] and generates the RXF interrupt (if enabled). The channel also

increments the abort sequence counter. The CRC and nonoctet error status conditions are not

checked on aborted frames. The receiver then enters hunt mode. When an abort sequence is

received, the user is given no indication that an HDLC controller is not currently receiving a frame.

Nonoctet

Aligned Frame

When this error occurs, the channel writes the received data to the data buffer, closes the buffer,

sets the Rx nonoctet aligned frame bit RxBD[NO], and generates the RXF interrupt (if it is enabled).

The CRC error status should be disregarded on nonoctet frames. After a nonoctet aligned frame is

received, the receiver enters hunt mode. An immediate back-to-back frame is still received. The

nonoctet data portion may be derived from the last byte in the buffer by finding the least-significant

set bit, which marks the end of valid data as follows:

msb

lsb

Valid data

1000

CRC Error

When this error occurs, the channel writes the received CRC to the data buffer, closes the buffer,

sets RxBD[CR], and generates the RXF interrupt (if it is enabled). The channel also increments the

CRC error counter. After receiving a frame with a CRC error, the receiver enters hunt mode. An

immediate back-to-back frame is still received. CRC checking cannot be disabled, but the CRC error

can be ignored if checking is not required.

MPC8280 Datasheet(PDF) 1269 Page - Freescale Semiconductor, Inc

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