MPC8280 datasheet(1283/1386 Pages) FREESCALE

1283 / 1386 page

FCC Transparent Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

38-3

The receiver synchronizes on the synchronization pattern located in the FDSR. For instance, if an 8-bit

SYNC is selected, reception begins as soon as these eight bits are received, beginning with the first bit

following the 8-bit SYNC. This effectively links the transmitter synchronization to the receiver

synchronization.

38.3.2

External Synchronization Signals

If GFMR[SYNL] = 00, an external signal is used to begin the sequence. CTS is used for the transmitter

and CD is used for the receiver; these signals share the following sampling options.

•

The pulse/envelope option determines whether CD or CTS need to be asserted only once to begin

reception/transmission or whether they must be asserted and stay that way for the duration of the

transparent frame. This option is controlled by the CDP and CTSP bits of the GFMR. If the user

expects a continuous stream of data without interruption, the pulse option should be used.

However, if the user needs to identify frames of transparent data, the envelope mode of the these

signals should be used. Note that the first bit of a frame is transmitted as zero every time RTS is

asserted before CTS is asserted (GFMR[CTSS] = 1); subsequent data bits are sent accurately.

Similarly, if CTS is in pulse mode (GFMR[CTSP] = 1), only the first frame is affected. If CTS is

not in pulse mode (GFMR[CTSP] = 0), every frame is affected separately. Note that if NRZI

encoding is used (GFMR[TENC]=01), RTS must be asserted before CTS, or else the first bit of the

frame might be corrupted.

•

The sampling option determines the delay between CD and CTS being asserted and the resulting

action by the FCC. These signals can be assumed to be asynchronous to the data and then internally

synchronized by the FCC, or they can be assumed to be synchronous to the data giving faster

operation. This option allows the RTS of one FCC to be connected to the CD of another FCC (on

another MPC8280) and to have the data synchronized and bit aligned. It is also an option to link

the transmitter synchronization to the receiver synchronization.

When working with the FCC receiver in envelope mode, RTS should be asserted for at least 3 clock cycles

between frames. Otherwise, the receiver cannot recognize the start of a new frame. Diagrams for the

pulse/envelope and sampling options are in Section 30.11, “FCC Timing Control.”

MPC8280 Datasheet(PDF) 1283 Page - Freescale Semiconductor, Inc