MPC8280 datasheet(1286/1386 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

39-2

Freescale Semiconductor

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Supports back-to-back character transmission and reception

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Master or slave SPI modes supported

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Multimaster environment support

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Continuous transfer mode for automatic scanning of a peripheral

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Supports maximum clock rates of 25 in master mode and 50 MHz in slave mode, assuming a

100-MHz system clock

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Independent programmable baud rate generator

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Programmable clock phase and polarity

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Open-drain outputs support multimaster configuration

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Local loopback capability for testing

39.2

SPI Clocking and Signal Functions

The SPI can be configured as a slave or as a master in single- or multiple-master environments. The master

SPI generates the transfer clock SPICLK using the SPI baud rate generator (BRG). The SPI BRG takes its

input from BRGCLK, which is generated in the MPC8280 clock synthesizer.

SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and

polarity can be configured with SPMODE[CI, CP]. SPI signals can also be configured as open-drain to

support a multimaster configuration in which a shared SPI signal is driven by the MPC8280 or an external

SPI device.

The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave

devices. Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input

for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to

communicate with one another using a common hardware configuration.

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When the SPI is a master, SPICLK is the clock output signal that shifts received data in from

SPIMISO and transmitted data out to SPIMOSI. SPI masters must output a slave select signal to

enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI’s

SPISEL while it is master causes an error.

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When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and

transmitted data out through SPIMISO. SPISEL is the enable input to the SPI slave. In a

multimaster environment, SPISEL (always an input) is used to detect an error when more than one

master is operating.

As described in Chapter 41, “Parallel I/O Ports,” SPIMISO, SPIMOSI, SPICLK, and SPISEL are

multiplexed with port D[16–19] signals, respectively. They are configured as SPI signals through the port

D signal assignment register (PDPAR) and the port D data direction register (PDDIR), specifically by

setting PDPAR[DDn] and PDDIR[DRn].

39.3

Configuring the SPI Controller

The SPI can be programmed to work in a single- or multiple-master environment. This section describes

SPI master and slave operation in a single-master configuration and then discusses the multi-master

environment.

MPC8280 Datasheet(PDF) 1286 Page - Freescale Semiconductor, Inc

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