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MPC8280 Datasheet(PDF) 1294 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 1294 Page - Freescale Semiconductor, Inc

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Serial Peripheral Interface (SPI)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
39-10
Freescale Semiconductor
39.4.3
SPI Command Register (SPCOM)
The SPI command register (SPCOM), shown in Figure 39-8, is used to start SPI operation.
Table 39-4 describes the SPCOM fields.
39.5
SPI Parameter RAM
The SPI parameter RAM area is similar to the SCC general-purpose parameter RAM. The CP accesses the
SPI parameter table using a user-programmed pointer (SPI_BASE) located in the parameter RAM; see
Section 14.5.2, “Parameter RAM.” The SPI parameter table can be placed at any 64-byte aligned address
in the dual-port RAM’s general-purpose area (banks 1–8, 11 and 12). Some parameter values must be
user-initialized before the SPI is enabled; the CP initializes the others. Once initialized, parameter RAM
values do not usually need to be accessed. They should be changed only when the SPI is inactive.
Table 39-5 shows the memory map of the SPI parameter RAM.
5
BSY
Busy. Set after the first character is received but discarded because no Rx buffer is available.
6
TXB
Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7
RXB
Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.
01
7
Field
STR
—
Reset
0000_0000
R/W
Write Only
Addr
0x11AAD
Figure 39-8. SPCOM—SPI Command Register
Table 39-4. SPCOM Field Descriptions
Bits
Name
Description
0
STR
Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from
the Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load
the Tx data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is
asserted. STR is cleared automatically after one system clock cycle.
1–7
—
Reserved and should be cleared.
Table 39-3. SPIE/SPIM Field Descriptions (continued)
Bits
Name
Description



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