MPC8280 datasheet(1293/1386 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

39-9

Example 2

with LEN=7 (data size=8), the following data is selected:

msb

ghij_klmn__opqr_stuv

lsb

the data string is selected:

msb

ghij_klmn__opqr_stuv

lsb

with REV=0, the string transmitted, a byte at a time with lsb first is:

first

nmlk_jihg__vuts_rqpo

last

with REV=1, the string is byte reversed and transmitted, a byte at a time, with lsb

first:

first

ghij_klmn__opqr_stuv

last

Example 3

with LEN=0xC (data size=13), the following data is selected:

msb

ghij_klmn__xxxr_stuv

lsb

the data string selected is:

msb

r_stuv__ghij_klmn

lsb

with REV=0, the string transmitted, a byte at a time with lsb first is:

first

vuts_r__nmlk_jihg

last

with REV=1, the string is half-word reversed:

msb

nmlk_jihg__vuts_r

lsb

and transmitted a byte at a time with lsb first:

first

ghij_klmn__r_stuv

last

39.4.2

SPI Event/Mask Registers (SPIE/SPIM)

The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI. When an

event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by writing a 1—writing 0 has

no effect. Setting a bit in the SPI mask register (SPIM) enables and clearing a bit masks the corresponding

interrupt. Unmasked SPIE bits must be cleared before the CP clears internal interrupt requests. Figure 39-7

shows both registers.

Table 39-3 describes the SPIE/SPIM fields.

01234567

Field

—

MME

TXE

—

BSY

TXB

RXB

Reset

0000_0000

R/W

Addr

0x11AA6 (SPIE); 0x11AAA (SPIM)

Figure 39-7. SPIE/SPIM—SPI Event/Mask Registers

Table 39-3. SPIE/SPIM Field Descriptions

Bits

Name

Description

0–1

—

Reserved, should be cleared.

MME

Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.

TXE

Tx error. Set when an error occurs during transmission.This event is not maskable via the TxBD[I]

bit.

—

Reserved, should be cleared.

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