BMP585 datasheet(43/71 Pages) BOSCH

43 / 71 page

Bosch Sensortec

| BST-BMP585-DS003-02

43 | 71

Document number: BST-BMP585-DS003-02

as well as in the event of applications for industrial property rights

0x8A

Direct

SETMRL

Set max read length

0x8B

Direct

GETMWL

Get max write length

0x8C

Direct

GETMRL

Get max read length

0x8D

Direct

GETPID

Get provisional ID

0x8E

Direct

GETBCR

Get bus characteristics register

0x8F

Direct

GETDCR

Get device characteristics register

0x90

Direct

GETSTATUS Get device status

0x91

Direct

GETACCMST Get accept mastership

0x93

Direct

SETBRGTGT Get bridge status

0x94

Direct

GETMXDS

Get max data speed

0x95

Direct

GETHDRCAP Get HDR capability

0x98

Direct

SETXTIME

Exchange timing information

0x99

Direct

GETXTIME

Get timing information

a. CCC SETDASA can be used once to assign the dynamic address. If the address shall be changed without resetting or power-cycling the device, CCC SETNEWDA must be used.

5.7.4 I3C SDR Operations

The BMP585‘s I3C follows the standard I3C specification and defines the private protocol part to meet the data transfer

requirements.

The address for all read and write transactions can be set according to the timing diagram in Figure 18. The 7-bit address

is allocated in byte section right after the dynamic address transmission. There is a 1-bit dummy content and the address

transfers from MSB to LSB.

The read data transfer itself is shown in timing diagrams in Figure 19 for single byte reads, and in Figure 20 for read bursts.

Data is provided in 8-bit granularity. In both read and write operations, the data transfer bit order is from MSB to LSB.

A read data transfer may be followed directly by another read data transfer, without setting a new address. In this case the

automatic address increment feature of BMP585 increments the addresses for all subsequent data reads until a new

address is set.

Figure 18: I3C address setting timing diagram

Figure 19: I3C SDR read timing diagram (single byte)

Figure 20: I3C SDR read timing diagram (multiple bytes)

The write transaction (see Figure 21) always contains the target address before the data content is transferred. In case

multiple byte datum content are sent out by host, the internal address pointer is incremented automatically, and the content

will be written into the preceding address byte by byte.

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