PIC16F18323-ESLASHSLSQTP datasheet(112/442 Pages) MICROCHIP

112 / 442 page

PIC16(L)F18313/18323

DS40001799A-page 112

Preliminary

 2015 Microchip Technology Inc.

10.4.2

NVM UNLOCK SEQUENCE

The unlock sequence is a mechanism that protects the

NVM from unintended self-write programming or

erasing. The sequence must be executed and

completed

without

interruption

successfully

complete any of the following operations:

• Program Flash Memory Row Erase

• Load of Program Flash Memory write latches

• Write of Program Flash Memory write latches to

Program Flash Memory

• Write of Program Flash Memory write latches to

User IDs

• Write to EEPROM

The unlock sequence consists of the following steps

and must be completed in order:

• Write 55h to NVMCON2

• Write AAh to NMVCON2

• Set the WR bit of NVMCON1

Once the WR bit is set, the processor will stall internal

operations until the operation is complete and then

resume with the next instruction.

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

FIGURE 10-2:

NVM UNLOCK

SEQUENCE FLOWCHART

EXAMPLE 10-2:

NVM UNLOCK SEQUENCE

Note:

The two NOP instructions after setting the

WR bit that were required in previous

devices

are

not

required

for

PIC16(L)F18313/18323

devices.

See

Figure 10-2.

Start Unlock Sequence

Write 55h to NVMCON2

Write AAh to NVMCON2

Initiate Write or Erase operation

(WR = 1)

NOP instruction

(Not Required for 18313/18323

devices)

End

Operation

NOP instruction

(Not required for 18313/18323

devices)

BANKSEL

NVMCON1

BSF

NVMCON1,WREN

; Enable write/erase

MOVLW

55h

; Load 55h

BCF

INTCON,GIE

; Recommended so sequence is not interrupted

MOVWF

NVMCON2

; Step 1: Load 55h into NVMCON2

MOVLW

AAh

; Step 2: Load W with AAh

MOVWF

NVMCON2

; Step 3: Load AAh into NVMCON2

BSF

NVMCON1,WR

; Step 4: Set WR bit to begin write/erase

BSF

INTCON,GIE

; Re-enable interrupts

Note 1:

Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order

shown.

Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

PIC16F18323-E/SLSQTP Datasheet(PDF) 112 Page - Microchip Technology

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