PIC16F570 datasheet(24/134 Pages) MICROCHIP

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PIC16F527

DS40001652C-page 24

 2012-2014 Microchip Technology Inc.

5.1.2

WRITING TO FLASH DATA

MEMORY

Once a cell is erased, new data can be written.

Program execution is suspended during the write cycle.

The self-write operation writes four bytes of data at one

time. The data must first be loaded into four write

latches. Once the write latches are loaded, the data will

be written to Flash data memory.

The self-write sequence is shown below.

The following self-write sequence must be performed

for four bytes to be written.

Load EEADR with the address.

Load EEDATA with the data to be written.

Set the WREN bit to enable write access to the

array.

Disable interrupts.

Set the WR bit to load the data into the write

latch.

Steps 1 through 5 are repeated three more times

to load the remaining write latches.

On the fourth and final loop, the EEADR register will

contain an address in the format of b’00xxxx11.

When the WR bit is set for the final time, the processor

will recognize that this is the last write latch to be

loaded, and will automatically load the write latch and

then, immediately perform the Flash data memory

write of all four bytes.

The specific sequence of setting the WREN bit and

setting the WR bit must be executed to properly initiate

each load of the write latches and the write to Flash

data memory.

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

Sample code that follows this procedure is included in

Example 5-3.

EXAMPLE 5-3:

WRITING TO FLASH DATA

MEMORY

5.2

Write/Verify

Depending on the application, good programming

practice may dictate that data written to the Flash data

memory be verified. Example 5-4 is an example of a

write/verify.

EXAMPLE 5-4:

WRITE/VERIFY OF FLASH

DATA MEMORY

Note 1: The FREE bit may be set by any

command normally used by the core.

However, the WREN and WR bits can

only be set using a series of BSF com-

mands, as documented in Example 5-1.

No other sequence of commands will

work, no exceptions.

2: Bits <5:3> of the EEADR register indicate

which row is to be erased.

Note 1: Only a series of BSF commands will work

to enable the memory write sequence

documented in Example 5-3. No other

sequence of commands will work, no

exceptions.

2: For reads, erases and writes to the Flash

data memory, there is no need to insert a

NOP into the user code as is done on mid-

range

devices.

The

instruction

immediately

following

the

“BSF

EECON,WR/RD” will be fetched and

executed properly.

MOVLB 0x01

;SWITCH TO BANK 1

MOVLW 0x04

;LOAD 4 DATA BYTES

MOVWF LoopCount

;WRITE LOOP

WRITE_LOOP

;VARIABLE STORED

MOVLW EE_ADR_WRITE

;LOAD ADDRESS TO

;WRITE

MOVWF EEADR

;INTO EEADR

;REGISTER

MOVLW EE_DATA_TO_WRITE;LOAD DATA TO

MOVWF EEDATA

;INTO EEDATA

;REGISTER

BSF

EECON,WREN

;ENABLE WRITES

BSF

EECON,WR

;LOAD WRITE LATCH

BTFSC LoopCount

;TEST IF 4th BYTE

GOTO

WRITE_LOOP

;

;WRITE IS DONE

;

MOVF

EEDATA, W

;EEDATA has not changed

;from previous write

BSF

EECON, RD

;Read the value written

XORWF

EEDATA, W

;

BTFSS

STATUS, Z

;Is data the same

GOTO

WRITE_ERR

;No, handle error

;Yes, continue

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