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STM32L4S5AI Datasheet(PDF) 217 Page - STMicroelectronics

Part # STM32L4S5AI
Description  Ultra-low-power Arm® Cortex®-M4 32-bit MCUFPU, 150DMIPS, up to 2MB Flash, 640KB SRAM, LCD-TFT & MIPI DSI, AESHASH
PDF  275 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L4S5AI Datasheet(HTML) 217 Page - STMicroelectronics

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STM32L4S5xx, STM32L4S7xx and STM32L4S9xx
Electrical characteristics
250
Figure 38. SPI timing diagram - slave mode and CPHA = 0
tdis(SO) Data output disable time Slave mode
9
-
16
ns
tv(SO)
Data output valid time
Slave mode
2.7 V < VDD < 3.6 V
Voltage Range V1
-13
15
ns
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V1
-10
23
Slave mode
1.71 V < VDD < 3.6 V
Voltage Range V2
-13
25
Slave mode
1.08 V < VDD < 1.32 V(3)
-29
39
tv(MO)
Master mode
-
2
4
th(SO)
Data output hold time
Slave mode 1.71 V < VDD < 3.6 V
7
-
-
Slave mode 1.08 < VDD < 1.32 V(3)
26
-
-
th(MO)
Master mode
1
-
-
1. Guaranteed by characterization results.
2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into
SCK low or high-phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
3. SPI mapped on Port G.
Table 92. SPI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max(2)
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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