STW4810 datasheet(52/78 Pages) STMICROELECTRONICS

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Electrical and timing characteristics

STw4810

52/78

5.3.4

VIO_VMEM DC/DC step-down converter

VCORE regulator in sleep mode (SLEEP= ‘1’)

VBAT

Input power supply Battery voltage

2.7

3.6

4.8

VRIPPLE

VCORE output

voltage ripple

mVpp

LIR

Line regulation

VBAT: [2.7; 4.8]V

LDR

Load regulation

IOUT: [0.1; 5] mA

IOUT

VCORE output

current

5mA

PEFF

Power efficiency

VBAT= 3.6 V

IOUT: [0.1; 5] mA

Quiescent current

IOUT = 0 mA

µA

LIRT

Transient line

regulation

Δ VBAT= 300 mV

tR = tF = 10 µs

7mV

Guaranteed by design

Table 38.

VCORE DC/DC step-down converter (continued)

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

Table 39.

VIO_VMEM DC/DC step-down converter

Symbol

Description

Test conditions

Min.

Typ.

Max.

Units

VIO_VMEM regulator in normal mode (SLEEP = ‘0’)

VBAT

Input power supply Battery voltage

2.7

3.6

4.8

VOUT

Output voltage (1)

-3%

1.8

+3%

VRIPPLE

Output ripple

mVpp

LIR

Line regulation

VBAT: [2.7; 4.8]V

LDR

(2)

Load regulation

IOUT: [0.1; 600] mA

IOUT

Output current

600

PEFF

Power efficiency

VBAT = 3.6 V,

VIO = 1.8 V

IOUT= 100 mA

ISHORT

Short circuit

current limitation(2)

0.9

1.2

1.4

Quiescent current

IOUT = 0 mA

130

250

µA

PSRR(2)

Power supply

rejection

Vpp = 0.3 V

[0; 20] kHz

LIRT

Transient line

regulation

ΔVBAT = 300 mV

tR = tF = 10 µs

LDRT

Transient load

regulation

IOUT= [1; 600] mA

tR = tF = 100 ns

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