MSP430F6733IPZ datasheet(45/154 Pages) TI2

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MSP430F6736

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MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720

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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018

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Specifications

Table 5-29 lists the supported clock frequencies of the eUSCI in SPI master mode.

Table 5-29. eUSCI (SPI Master Mode) Clock Frequency

PARAMETER

CONDITIONS

VCC

MIN

MAX

UNIT

feUSCI

eUSCI input clock frequency

Internal: SMCLK or ACLK,

Duty cycle = 50% ±10%

fSYSTEM

MHz

Table 5-30 lists the switching characteristics of the eUSCI in SPI master mode.

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-13 and Figure 5-14.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

13 and Figure 5-14.

Table 5-30. eUSCI (SPI Master Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

tSTE,LEAD

STE lead time, STE active to clock

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

150

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

150

tSTE,LAG

STE lag time, Last clock to STE

inactive

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

200

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

200

tSTE,ACC

STE access time, STE active to SIMO

data out

UCSTEM = 0, UCMODEx = 01 or 10

2 V

3 V

UCSTEM = 1, UCMODEx = 01 or 10

2 V

3 V

tSTE,DIS

STE disable time, STE inactive to

SIMO high impedance

UCSTEM = 0, UCMODEx = 01 or 10

2 V

3 V

UCSTEM = 1, UCMODEx = 01 or 10

2 V

3 V

tSU,MI

SOMI input data setup time

2 V

3 V

tHD,MI

SOMI input data hold time

2 V

3 V

tVALID,MO

SIMO output data valid time(2)

UCLK edge to SIMO valid, CL = 20 pF

2 V

3 V

tHD,MO

SIMO output data hold time(3)

CL = 20 pF

2 V

3 V

MSP430F6733IPZ Datasheet(PDF) 45 Page - Texas Instruments

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