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MSP430F6733IPZ Datasheet(PDF) 95 Page - Texas Instruments |
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MSP430F6733IPZ Datasheet(HTML) 95 Page - Texas Instruments |
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95 / 154 page ![]() P1.0/PM_TA0.0/VeREF-/A2 P1.1/PM_TA0.1/VeREF+/A1 P1SEL.x 1 0 P1DIR.x P1IN.x P1IRQ.x EN To Port Mapping 1 0 From Port Mapping P1OUT.x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x 1 0 DVSS DVCC 1 P1DS.x 0: Low drive 1: High drive D From Port Mapping Pad Logic To ADC10_A INCHx = y Bus Keeper To and from Reference Direction 0: Input 1: Output P1REN.x P1MAP.x = PMAP_ANALOG 95 MSP430F6736 , MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730 MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720 www.ti.com SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018 Submit Documentation Feedback Product Folder Links: MSP430F6736 MSP430F6735 MSP430F6734 MSP430F6733 MSP430F6731 MSP430F6730 MSP430F6726 MSP430F6725 MSP430F6724 MSP430F6723 MSP430F6721 MSP430F6720 Detailed Description Copyright © 2011–2018, Texas Instruments Incorporated 6.12 Input/Output Diagrams 6.12.1 Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger (MSP430F67xxIPZ and MSP430F67xxIPN) Figure 6-2 shows the port diagram. Table 6-58 summarizes the selection of the pin functions. Figure 6-2. Port P1 (P1.0 and P1.1) Diagram (MSP430F67xxIPZ and MSP430F67xxIPN) |
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