MSP430F6733IPZ datasheet(13/154 Pages) TI2

13 / 154 page

MSP430F6736

, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730

MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720

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SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018

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Terminal Configuration and Functions

Table 4-3. Terminal Functions, PZ Package (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

NO.

(3)

The pins VDSYS and DVSYS must be connected externally on the board for proper device operation.

(4)

VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, CVCORE.

VDSYS(3)

Digital power supply selected between DVCC, AUXVCC1, AUXVCC2. Connect

recommended capacitor value of CVSYS (see Table 5-18).

DVCC

Digital power supply

DVSS

Digital ground supply

VCORE(4)

Regulated core power supply (internal use only, no external current loading)

XIN

Input terminal for crystal oscillator

XOUT

Output terminal for crystal oscillator

AUXVCC3

Auxiliary power supply AUXVCC3 for back up subsystem

P1.4/PM_UCA1RXD/

PM_UCA1SOMI/LCDREF/R13

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART receive data; eUSCI_A1 SPI slave out/master in

External reference voltage input for regulated LCD voltage

Input/output port of third most positive analog LCD voltage (V3 or V4)

P1.5/PM_UCA1TXD/

PM_UCA1SIMO/R23

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A1 UART transmit data; eUSCI_A1 SPI slave in/master out

Input/output port of second most positive analog LCD voltage (V2)

LCDCAP/R33

I/O

LCD capacitor connection

Input/output port of most positive analog LCD voltage (V1)

CAUTION: This pin must be connected to DVSS if not used.

P8.4/TA1.0

I/O

General-purpose digital I/O

Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output

P8.5/TA1.1

I/O

General-purpose digital I/O

Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output

COM0

LCD common output COM0 for LCD backplane

COM1

LCD common output COM1 for LCD backplane

COM2

LCD common output COM2 for LCD backplane

COM3

LCD common output COM3 for LCD backplane

P1.6/PM_UCA0CLK/COM4

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_A0 clock input/output

LCD common output COM4 for LCD backplane

P1.7/PM_UCB0CLK/COM5

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 clock input/output

LCD common output COM5 for LCD backplane

P2.0/PM_UCB0SOMI/

PM_UCB0SCL/COM6

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: eUSCI_B0 SPI slave out/master in; eUSCI_B0 I2C clock

LCD common output COM6 for LCD backplane

MSP430F6733IPZ Datasheet(PDF) 13 Page - Texas Instruments

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