MSP430F6733IPZ datasheet(78/154 Pages) TI2

78 / 154 page

MSP430F6736

, MSP430F6735, MSP430F6734, MSP430F6733, MSP430F6731, MSP430F6730

MSP430F6726, MSP430F6725, MSP430F6724, MSP430F6723, MSP430F6721, MSP430F6720

SLAS731D – DECEMBER 2011 – REVISED SEPTEMBER 2018

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Detailed Description

6.11.15 TA0

TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support

multiple capture/compares, PWM outputs, and interval timing (see Table 6-13). TA0 also has extensive

interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each

of the capture/compare registers.

Table 6-13. TA0 Signal Connections

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PM_TACLK

TACLK

Timer

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLK

INCLK

PM_TA0.0

CCI0A

CCR0

TA0

PM_TA0.0

DVSS

CCI0B

DVSS

GND

DVCC

VCC

PM_TA0.1

CCI1A

CCR1

TA1

PM_TA0.1

ACLK (internal)

CCI1B

ADC10_A (internal)

ADC10SHSx = {1}

DVSS

GND

SD24_B (internal)

SD24SCSx = {1}

DVCC

VCC

PM_TA0.2

CCI2A

CCR2

TA2

PM_TA0.2

DVSS

CCI2B

DVSS

GND

DVCC

VCC

6.11.16 TA1

TA1 is a 16-bit timer/counter (Timer_A type) with two capture/compare registers. TA1 can support multiple

capture/compares, PWM outputs, and interval timing (see Table 6-14). TA1 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the

capture/compare registers.

Table 6-14. TA1 Signal Connections

DEVICE INPUT SIGNAL

MODULE INPUT NAME

MODULE BLOCK

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

PM_TACLK

TACLK

Timer

ACLK (internal)

ACLK

SMCLK (internal)

SMCLK

PM_TACLK

INCLK

PM_TA1.0

CCI0A

CCR0

TA0

PM_TA1.0

DVSS

CCI0B

DVSS

GND

DVCC

VCC

PM_TA1.1

CCI1A

CCR1

TA1

PM_TA1.1

ACLK (internal)

CCI1B

DVSS

GND

DVCC

VCC

MSP430F6733IPZ Datasheet(PDF) 78 Page - Texas Instruments

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