XM33C321ASPZR datasheet(46/113 Pages) TI2

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over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CL, eff

Integrated effective load capacitance(1)

tstart, LFXT LFXT start-up time

483

640

ILFXT

LFXT current consumption

XT1DRIVE=TBD, LOWCAP=TBD

200

Low frequency digital clock input (LFCLK_IN)

fLFIN

LFCLK_IN frequency (2)

SETUSEEXLF=1

29491

32768

36045

DCLFIN

LFCLK_IN duty cycle (2)

SETUSEEXLF=1

LFCLK Monitor

fFAULTLF

LFCLK monitor fault frequency (3)

MONITOR=1

2800

4200

8400

(1)

This includes parasitic bond and package capacitance (≈2pF per pin), calculated as CLFXIN×CLFXOUT/(CLFXIN+CLFXOUT), where CLFXIN

and CLFXOUT are the total capacitance at LFXIN and LFXOUT, respectively.

(2)

The digital clock input (LFCLK_IN) accepts a logic level square wave clock.

(3)

The LFCLK monitor may be used to monitor the LFXT or LFCLK_IN. It will always fault below the MIN fault frequency, and will never

fault above the MAX fault frequency.

7.9 Analog Specifications

7.9.1 ADC Specifications

7.9.1.1 ADC Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are

measured at 25

℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vin(ADC)

Analog input voltage range(1)

Applies to all ADC analog input pins

VDD

VR+

Positive ADC reference voltage

VR+ sourced from external reference pin (VREF+)

1.4

VDD

VR+ sourced from internal reference (VREF)

VREF

VR-

Negative ADC reference voltage

ADC sampling frequency

12-bit mode, External Reference, VDD ≥ 2.7V and VR+ ≥ 2.5V

9.4

Msps

12-bit mode, External Reference

7.25

Msps

I(ADC) (2)

Operating supply current

into VDD terminal

FS = 9.4 MSPS, Internal reference OFF, VR+ = VDD

2.8

FS = 4 MSPS, Internal reference OFF, VR+ = VDD

1.9

CS/H

ADC sample-and-hold capacitance

3.3

Rin

ADC input resistance

0.2

kΩ

ENOB

Effective number of bits

External reference, fIN = 100kHz, HW averaging 8x

12.3

bit

External reference, fIN = 100kHz

10.8

Internal reference, fIN = 100kHz, VR+ = VREF = 2.5V (3)

10.5

SNR

Signal-to-noise ratio

External reference, fIN = 100kHz

66.7

Internal reference, fIN = 100kHz, VR+ = VREF = 2.5V (3)

65.5

PSRRDC

Power supply rejection ratio, DC

External reference, VDD = VDD(MIN) to VDD(MAX)

VDD = VDD(MIN) to VDD(MAX)

Internal reference, VR+ = VREF = 2.5V (3)

PSRRAC

Power supply rejection ratio, AC

External reference, ΔVDD = 0.1 V at 1 kHz

ΔVDD = 0.1 V at 1 kHz

Internal reference, VR+ = VREF = 2.5V (3)

twakeup

ADC Wakeup Time

Assumes internal reference is active

VSupplyMon

Supply Monitor voltage divider

accuracy

ADC input channel: Supply Monitor (VDD/3), (VBAT/3)

(4)

–1.5

1.5

ISupplyMon

Supply Monitor voltage divider current

consumption

ADC input channel: Supply Monitor

(1)

The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.

(2)

The internal reference (VREF) supply current is not included in current consumption parameter I(ADC).

(3)

Minimum values based on characterization data

MSPM33C321A, MSPM33C3219

SLASFB6 – DECEMBER 2025

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XM33C321ASPZR Datasheet(PDF) 46 Page - Texas Instruments

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