XM33C321ASPZR datasheet(76/113 Pages) TI2

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8.13 Security and Cryptography

The device security comprises of the following peripherals

• Global Security Controller (GSC) for device security

• Advanced Encryption Standard (AES) accelerator

• Secure Hash Algorith (SHA256) accelerator with Hashed Message Authentication Control (HMAC) capability

• Public Key Accelerator (PKA) for assymetric cryptographic operations

• True Random Number Generator (TRNG)

• Keystore controller

• Cyclic Redundancy Check (CRC)

8.13.1 Global Security Controller (GSC)

The Global Security Controller (GSC) configures the secure and privilege attributes for the full device. The GSC

consists of multiple blocks that ensure the device's security and peripheral properties are seen same by all bus

initiators.

• Configures the secure and privilege attribute for the flash, SRAM and peripherals

• Configures the level of security and privilege state violation as NMI or bus-fault

• Configures the hide protection of flash sectors using watermark for start and end sector

• Logs security violation in the error aggregator module (EAM) for CPU to identify the initiator and destination

address

• Provides the result of DICE checksum for application to read

For more details, see the GSC chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference

Manual.

8.13.2 AESADV

The AES advanced (AESADV) accelerator module performs encryption and decryption of 128-bit data blocks

with a 128-bit or 256-bit key in hardware according to the advanced encryption standard (AES). AES is a

symmetric-key block cipher algorithm specified in FIPS PUB 197.

The AESADV accelerator features include:

• AES operation with 128-bit and 256-bit keys

• Key scheduling in hardware

• Enc/decrypt only modes: CBC, CFB-1, CFB-8, CFB-128, OFB-128, CTR/ICM

• Authentication only modes: CBC-MAC, CMAC

• Support for AES-CCM and AES-GCM modes

• AES-CCM and AES-GCM modes support continuation with hold/resume of payload data

• 32-bit word access to provide key data, input data, and output data

• AESADV ready interrupt

• DMA triggers for input/output data

• Supported in RUN and SLEEP (see the Operating Modes section of the device technical reference manual)

For more details, see the AESADV chapter of the MSPM33C3x 160-MHz Microcontrollers Technical Reference

Manual.

8.13.3 SHA256

The SHA256 provides hardware-acclerated hash functions. These has functions can generate a condensed

representation of a message or a data file call digest which can then be used to verify the message integrity.

• SHA-2 (SHA-224 and SHA-256) algorithm compliant with the FIPS 180-3 standard

• Hash message authentication code (HMAC) operation

• Hashing of 0 to 233 bytes of data SHA-224, or SHA-256 hash algorithm at byte granularity

• Host-assisted HMAC key preprocessing for HMAC keys larger than 64 bytes

• HMAC from precomputes (inner/outer digest) for improved performance on small blocks

• Supports DMA for efficient data transfer

MSPM33C321A, MSPM33C3219

SLASFB6 – DECEMBER 2025

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XM33C321ASPZR Datasheet(PDF) 76 Page - Texas Instruments

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