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XM33C321ASPZR Datasheet(PDF) 62 Page - Texas Instruments

Part # XM33C321ASPZR
Description  MSPM33C321x Mixed-Signal Microcontrollers
PDF  113 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

XM33C321ASPZR Datasheet(HTML) 62 Page - Texas Instruments

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Table 8-1. Supported Functionality by Operating Modes (continued)
OPERATING MODE
RUN
SLEEP
STOP
STANDBY
SHUTDOWN
VBAT
RTC
OPT
IWDT
OPT
LFXT
OPT
BACKUP_REG
OPT
TAMPER
OPT
IOMUX and IO Wakeup
EN
DIS w/ WAKE
Wake Sources
N/A
ANY IRQ
PD0 IRQ, LFSS
IRQ
PD0 IRQ, LFSS
IRQ
IOMUX, NRST,
SWD
8.3 Device Memory Map
8.3.1 Memory Organization
Table 8-2 summarizes the platform memory map of the device.
Table 8-2. Platform Memory Map
MEMORY REGION
SUBREGION
MSPM33C32xA
MSPM33C32x9
Flash
Non-Secure
0x0000.0000 to 0x00FF.FFFF
0x0000.0000 to 0x007F.FFFF
Secure
0x1000.0000 to 0x10FF.FFFF
0x1000.0000 to 0x107F.FFFF
SRAM
Non-Secure
0x2000.0000 to 0x203F.FFFF
0x2000.0000 to 0x203F.FFFF
Secure
0x3000.0000 to 0x303F.FFFF
0x3000.0000 to 0x303F.FFFF
Peripheral
Non-Secure
0x4000.0000 to 0x4FFF.FFFF
0x4000.0000 to 0x4FFF.FFFF
Secure
0x5000.0000 to 0x5FFF.FFFF
0x5000.0000 to 0x5FFF.FFFF
Subsystem
Non-Secure Region 0
0x6000.0000 to 0x6FFF.FFFF
0x6000.0000 to 0x6FFF.FFFF
Secure Region 0
0x7000.0000 to 0x7FFF.FFFF
0x7000.0000 to 0x7FFF.FFFF
Data Flash Non Secure
0x8000.0000 to 0x8000.7FFF
0x8000.0000 to 0x8000.7FFF
Non-Secure Region 1
0x8008.0000 to 0x8FFF.FFFF
0x8000.8000 to 0x8FFF.FFFF
Data Flash Secure
0x9000.0000 to 0x9000.7FFF
0x9000.0000 to 0x9000.7FFF
Secure Region 1
0x9000.8000 to 0x9FFF.FFFF
0x9000.8000 to 0x9FFF.FFFF
Non-Secure Region 2
0xA000.0000 to 0xAFFF.FFFF
0xA000.0000 to 0xAFFF.FFFF
Secure Region 2
0xB000.0000 to 0xBFFF.FFFF
0xB000.0000 to 0xBFFF.FFFF
Non-Secure Region 3
0xC000.0000 to 0xCFFF.FFFF
0xC000.0000 to 0xCFFF.FFFF
Secure Region 3
0xD000.0000 to 0xDFFF.FFFF
0xD000.0000 to 0xDFFF.FFFF
System PPB
0xE000.0000 to 0xE00F.FFFF
0xE000.0000 to 0xE00F.FFFF
8.3.2 Peripheral Memory Map
Table 8-3 lists the available peripherals and the register base address for each in the secure and non-secure
regions.
Table 8-3. Peripherals Memory Map
Peripheral Name
Non-Secure Base Address Secure Base Address
Size
HSADC0.CONFIG
0x4000.0000
0x5000.0000
0x2000
HSADC1.CONFIG
0x4000.2000
0x5000.2000
0x2000
HSADC0.FIFO
0x4000.5000
0x5000.5000
0x1000
HSADC1.FIFO
0x4000.7000
0x5000.7000
0x1000
TIMA0_0
0x4001.0000
0x5001.0000
0x2000
TIMA0_1
0x4001.2000
0x5001.2000
0x2000
DMA0
0x4002.0000
0x5002.0000
0x2000
DMA1
0x4002.2000
0x5002.2000
0x2000
MSPM33C321A, MSPM33C3219
SLASFB6 – DECEMBER 2025
www.ti.com
62
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Copyright © 2025 Texas Instruments Incorporated
Product Folder Links: MSPM33C321A MSPM33C3219



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