FN7560 datasheet(11/21 Pages) RENESAS

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ISL33001, ISL33002, ISL33003

FN7560 Rev 6.02

Page 11 of 20

Oct 2, 2023

Application Information

The ISL33001, ISL33002, ISL33003 ICs are 2-Wire Bidirectional

Bus Buffers designed to drive heavy capacitive loads in

open-drain/open-collector systems. The ISL33001, ISL33002,

ISL33003 incorporate rise time accelerator circuitry that

improves the rise time for systems that use a passive pull-up

resistor for logic HIGH. These devices also feature hot swapping

circuitry for applications that require hot insertion of boards into

a host system (i.e., servers racks and I/O card modules). The

ISL33001 features a logic output flag (READY) that signals the

status of the buffer and an EN pin to enable or disable the buffer.

The ISL33002 features two separate supply pins for voltage level

shifting on the I/O pins and a logic input to disable the rise time

accelerator circuitry. The ISL33003 features an EN pin and the

level shifting functionality.

I2C and SMBUS Compatibility

The ISL33001, ISL33002, ISL33003 ICs are I2C and SMBUS

compatible devices, designed to work in open-drain/open-collector

bus environments. The ICs support both clock stretching and bus

arbitration on the SDA and SCL pins. They are designed to operate

from DC to more than 400kHz, supporting Fast Mode data rates of

the I2C specification.In addition, the buffer rise time accelerators

are designed to increase the capacitive drive capability of the bus.

With careful choosing of components, driving a bus with the I2C

specified maximum bus capacitance of 400pF at 400kHz data rate

is possible.

Start-Up Sequencing and Hot Swap Circuitry

The ISL33001, ISL33002, ISL33003 buffers contain

undervoltage lock out (UVLO) circuitry that prevents operation of

the buffer until the IC receives the proper supply voltage. For

VCC1 and VCC2, this voltage is approximately 1.8V on the rising

edge of the supply voltage. Externally driven signals at the

SDA/SCL pins are ignored until the device supply voltage is

above 1.8V. This prevents communication errors on the bus until

the device is properly powered up. The UVLO circuitry is also

triggered on the falling edge when the supply voltage drops

below 1.7V.

Once the IC comes out of the UVLO state, the buffer remains

disconnected until it detects a valid connection state. A valid

connection state is either a BUS IDLE condition (see Figure 4) or a

STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high)

along with the SCL_OUT and SDA_OUT pins being logic high.

Note: For the ISL33001 and ISL33003 with EN pins, after coming

out of UVLO, there will be an additional delay from the enable

circuitry if the EN pin voltage is not rising at the same time as the

supply pins (see Figure 3) before a valid connection state can be

established.

Coming out of UVLO but prior to a valid connection state, the SDA

and SCL pins are pre-charged to 1V to allow hot insertion.

Because the bus at any time can be between 0V and VCC,

pre-charging the I/O pins to 1V reduces the maximum

differential voltage from the buffer I/O pin and the active bus.

The pre-charge circuitry reduces system disturbance when the IC

is hot plugged into a live back plane that may have the bus

communicating with other devices.

Note: For The ISL33001 and ISL33003 with EN pins, the

pre-charge circuitry is active only after coming out of UVLO and

having the device enabled.

Connection Circuitry

Once a valid connection condition is met, the buffer is active and

the input stage of the SDA/SCL pins is controlled by external

drivers. The output of the buffer will follow the input of the buffer.

The directionality of the IN/OUT pins are not exclusive

(bi-directional operation) and functionally behave identical to

each other. Being a two channel buffer, the SDA and SCL pins

also behave identically. In addition, the SDA and SCL portions of

the buffer are independent from each other. The SDA pins can be

driven in one direction while the SCL pins can be driven opposite.

Refer to Figure 10 for the operation of the bi-directional buffer.

When the input stage of the buffer on one side is driven low by an

external device, the output of the buffer drives an open-drain

transistor to pull the ‘output’ pin low. The ‘output’ pin will

continue to be held low by the transistor until the external driver

on the ‘input’ releases the bus.

To prevent the buffer from entering a latched condition where

both internal transistors are actively pulling the I/O pins low, the

buffer is designed to be active in only one direction. The buffer

logic circuitry senses, which input stage is being externally driven

low and sets that buffer to be the active one. For example,

referring to Figure 10, if SDA_OUT is externally driven low, buffer

U2 will be active and buffer U1 is inactive. M1 is turned on to

drive SDA_IN low, effectively buffering the signal from SDA_OUT

to SDA_IN. The low signal at the input of U1 will not turn M2 on

because U1 remains inactive, preventing a latch condition.

Buffer Output Low and Offset Voltage

By design, when a logic input low voltage is forced on the input of

the buffer, the output of the buffer will have an input to output

offset voltage. The output voltage of the buffer is determined by

Equation 1:

Where VOS is the buffer internal offset voltage, RPull-Up is the

pull-up resistance on the SDA/SCL pin to VCC and rON is the

ON-resistance of the buffer’s internal NMOS pull-down device.

The last term of the equation is the additional voltage drop

developed by sink current and the internal resistance of the

transistor. The VOS of the buffer can be determined by

Figures 21, 22 and is typically 40mV. Reducing the pull-up

resistor values increases the sink current and increases the

output voltage of the buffer for a given input low voltage

(Figures 19, through 22).

Rise Time Accelerators

The ISL33001, ISL33002, ISL33003 buffer rise time

accelerators on the SDA/SCL pins improve the transient

performance of the system. Heavy load capacitance or weak

pull-up resistors on an Open-Drain bus cause the rise time to be

excessively long, which leads to data errors or reduced data rate

performance. The rise time accelerators are only active on the

low-to-high transitions and provide an active constant current

source to slew the voltage on the pin quickly (Figure 23).

VOUT

VIN VOS

VCC/RPULL-UP rON





(EQ. 1)

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