AM2431BSDGHIALVR. datasheet(245/282 Pages) TI2

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To derive direction information, the lines on the disk are read out by two different photo-elements that "look"

at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is realized

with a reticle or mask that restricts the view of the photo-element to the desired part of the disk lines. As the

disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of phase from each other.

These are commonly called the quadrature QEPA and QEPB signals. The clockwise direction for most encoders

is defined as the QEPA channel going positive before the QEPB channel and vice versa.

The encoder wheel typically makes one revolution for every revolution of the motor or the wheel can be at a

geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from the

QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder

directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6KHz, so

by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the

motor.

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter

in the device TRM.

7.4.2.10 General-Purpose Memory Controller (GPMC)

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external

memory devices like:

• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices

• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash

devices

• NAND flash

• Pseudo-SRAM devices

For more information, see General-Purpose Memory Controller section in Peripherals chapter in the device

TRM.

7.4.2.11 I2C

The Inter-IC Bus (I2C) interface is implemented using the mshsi2c module. This peripheral implements the

multi-controller I2C bus, which allows serial transfer of 8-bit data to and from other I2C controller and target

devices, through a two-wire interface.

The I2C module supports the following main features:

• Compliant with Philips I2C specification version 2.1

• Supported Speeds:

– Standard mode (up to 100 K bits/s)

– Fast mode (up to 400 K bits/s)

– High-speed mode (up to 3.4M bits/s), I2C0 and MCU_I2C0 only

• Multi-controller transmitter and target receiver mode

• Multi-controller receiver and target transmitter mode

• Combined controller transmit/receive and receive/transmit modes

• 7-bit and 10-bit device addressing modes

• Built-in 32-byte FIFO for buffered read or write

• Programmable multi-target channel (responds to 4 separates addresses)

• Programmable clock generation

• Support for asynchronous wake-up

• One interrupt line

For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device

TRM.

7.4.2.12 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed

real-time control with a high level of security. CAN has high immunity to electrical interference and the ability

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