AM2431BSDGHIALVR. datasheet(247/282 Pages) TI2

247 / 282 page

7.4.2.16 OSPI

The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which

allows single, dual, quad or octal read and write access to external flash devices. This module has a memory

mapped register interface, which provides a direct memory interface for accessing data from external flash

devices, simplifying software requirements.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor

wishing to execute code directly from external flash memory), or in an indirect mode where the module is

set-up to silently perform some requested operation, signaling its completion via interrupts or status registers.

For indirect operations, data is transferred between system memory and external flash memory via an internal

SRAM which is loaded for writes and unloaded for reads by a device controller at low latency system speeds.

Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using

user programmable configuration registers.

For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device

TRM.

7.4.2.17 Peripheral Component Interconnect Express (PCIe)

The PCIe subsystem supports the following main features:

• Dual mode – root port (RP) or end point (EP) modes.

• 1-lane configuration with up to 5.0GT/lane.

• 62.5/125MHz operation on PIPE interface for Gen1/Gen2 respectively

• Constant 32-bit PIPE width for Gen1/Gen2 modes

• Maximum outbound payload size of 128 bytes

• Maximum inbound payload size of 128 bytes

• Maximum remote read request size of 4K bytes

• Maximum number of nonposted outstanding transactions: 8 on each VBUSM interface.

• Four virtual channels (4VC)

• Resizable BAR capability

• SRIS support

• Power Management

– L1 Power Management Substate support

– D1 support

– L1 Power Shutoff support

• Legacy, MSI, and MSI-X interrupt support

• 32 outbound address translation regions

• Precision time measurement (PTM)

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

7.4.2.18 Serializer/Deserializer (SerDes) PHY

Integrated in the MAIN domain is one instance of high-speed differential interface implemented with Serializer/

Deserializer (SerDes) Multi-protocol Multi-link PHY with the following main blocks:

• Single-lane SerDes PHY with common module for peripheral and Tx clocking handling

• Physical coding sub-block for data translation from/to the parallel interface, as well as data encoding/

decoding and symbol alignment

• MUX module for device interface multiplexing into a single SerDes lane (Tx and Rx)

• A wrapper for sending control and reporting status signals from the SerDes and muxes

For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.

7.4.2.19 Real Time Interrupt (RTI/WWDT)

This section describes the Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT)

functionality for the device.

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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