TMP9R01DGSSLASHEM datasheet(21/45 Pages) TI2

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7.5.1.2 Bus Definitions

The TMP9R01-SEP and TMP9R01-SP device are two-wire- and SMBus-compatible. Figure 7-8 and Figure 7-9

illustrate the timing for various operations on the TMP9R01-SEP and TMP9R01-SP devices. The bus definitions

are as follows:

Bus Idle:

Both SDA and SCL lines remain high.

Start Data

Transfer:

A change in the state of the SDA line (from high to low) when the SCL line is high defines

a start condition. Each data transfer initiates with a start condition.

Stop Data

Transfer:

A change in the state of the SDA line (from low to high) when the SCL line is high defines

a stop condition. Each data transfer terminates with a repeated start or stop condition.

Data Transfer:

The number of data bytes transferred between a start and stop condition is not limited and

is determined by the controller device. The receiver acknowledges the data transfer.

Acknowledge:

Each receiving device, when addressed, is obliged to generate an acknowledge bit. A

device that acknowledges must pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is stable low during the high period of the

acknowledge clock pulse. Take setup and hold times into account. On a controller receive,

data transfer termination can be signaled by the controller generating a not-acknowledge

on the last byte that is transmitted by the target.

Frame 1 Two Wire Device Address Byte

Frame 2 Pointer Register Byte

Host

Device

Frame 3 Data Byte 1

ACK By

Device

SDA

(Continued)

SCL

(Continued)

SCL

…

Start By

ACK By

SDA

…

(1)

Stop By

Host

Target address 1001100 is shown.

Figure 7-8. Two-Wire Timing Diagram for Write Word Format

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TMP9R01-SEP, TMP9R01-SP

SNIS238A – JULY 2025 – REVISED JULY 2026

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