Frame 1 Two Wire Device Address Byte

Frame 2 Pointer Register Byte

Host

Device

Device

9

SCL

1

9

1

1

Start By

ACK By

ACK By

SDA

0

0

1

1

0

0

P6

P7

P5

P4

P3

P2

P1

P0

(1)

W

/

R

Frame 3 Two Wire Device Address Byte

Frame 4 Data Byte 1 Read Register

Host

Device

Host

9

SCL

1

9

1

1

Start By

ACK By

NACK By

SDA

0

0

1

1

0

0

D6

D7

D5

D4

D3

D2

D1

D0

(1)

W

/

R

(Continued)

(Continued)

(2)

From

Device

A.

Target address 1001100 is shown.

B.

The controller must leave SDA high to terminate a single-byte read operation.

Figure 7-9. Two-Wire Timing Diagram for Single-Byte Read Format

7.5.1.3 Serial Bus Address

To communicate with the TMP9R01-SEP and TMP9R01-SP devices, the controller must first address target

devices using a target address byte. The target address byte consists of seven address bits and a direction bit

indicating the intent of executing a read or write operation. The TMP9R01-SEP and TMP9R01-SP devices allow

up to nine devices to be connected to the SMBus, depending on the A0, A1 pin connections as described in

Table 7-5. The A0 and A1 address pins must be isolated from noisy or high-frequency signals traces to avoid

false address settings when these pins are set to a float state.

Table 7-5. TMP9R01-SEP and TMP9R01-SP Target Address Options

A1 CONNECTION

A0 CONNECTION

TARGET ADDRESS

BINARY

HEX

GND

GND

1001 000

48

GND

Float

1001 001

49

GND

V+

1001 010

4A

Float

GND

1001 011

4B

Float

Float

1001 100

4C

Float

V+

1001 101

4D

V+

GND

1001 110

4E

V+

Float

1001 111

4F

V+

V+

1010 000

50

7.5.1.4 Read and Write Operations

Accessing a particular register on the TMP9R01-SEP and TMP9R01-SP devices are accomplished by writing

the appropriate value to the pointer register. The value for the pointer register is the first byte transferred after the

target address byte with the R/W bit low. Every write operation to the TMP9R01-SEP and TMP9R01-SP devices

require a value for the pointer register (see Figure 7-8).

When reading from the TMP9R01-SEP and TMP9R01-SP devices, the last value stored in the pointer register

by a write operation is used to determine which register is read by a read operation. To change which register is

TMP9R01-SEP, TMP9R01-SP

SNIS238A – JULY 2025 – REVISED JULY 2026

www.ti.com

22

Submit Document Feedback

Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: TMP9R01-SEP TMP9R01-SP