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TMP9R01DGS/EM Datasheet(PDF) 9 Page - Texas Instruments |
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TMP9R01DGS/EM Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 45 page ![]() 6.6 I2C Interface Timing At –55°C to 125°C and V+ = 1.7V to 3.6V, unless otherwise noted. FAST MODE FAST MODE PLUS HIGH-SPEED MODE UNIT MIN MAX MIN MAX MIN MAX f(SCL) SCL operating frequency 0.001 0.4 0.001 1 0.001 2.17 MHz t(BUF) Bus-free time between STOP and START conditions 1300 – 500 160 – ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 600 – 260 160 – ns t(SUSTA) Repeated START condition setup time 600 – 260 160 – ns t(SUSTO) STOP condition setup time 600 – 260 160 – ns t(HDDAT) Data hold time 0 900 0 150 0 130 ns t(SUDAT) Data setup time 100 – 50 20 – ns t(LOW) SCL clock low period 1300 – 500 320 – ns t(HIGH) SCL clock high period 600 – 260 60 – ns tF - SDA Data fall time 300 120 130 ns tF, tR - SCL Clock fall and rise time 300 – 120 40 ns tR Rise time for SCL ≤ 100kHz 1000 ms 6.7 Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A SUBGROUP DESCRIPTION TEMPERATURE ( ℃) 1 Static tests 25 2 Static tests 125 3 Static tests –55 4 Dynamics tests 25 5 Dynamics tests 125 6 Dynamics tests –55 7 Functional tests 25 8A Functional tests 125 8B Functional tests –55 9 Switching tests 25 10 Switching tests 125 11 Switching tests –55 www.ti.com TMP9R01-SEP, TMP9R01-SP SNIS238A – JULY 2025 – REVISED JULY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TMP9R01-SEP TMP9R01-SP |
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