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WM8959 Datasheet(PDF) 52 Page - Wolfson Microelectronics plc

Part # WM8959
Description  Mobile Multimedia DAC with Dual-Mode Class AB/D Speaker Driver
PDF  155 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8959 Datasheet(HTML) 52 Page - Wolfson Microelectronics plc

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WM8959
Pre-Production
w
PP, May 2008, Rev 3.1
52
DIGITAL TO ANALOGUE CONVERTER (DAC)
The WM8959 DACs receive digital input data from the DACDAT pin. The digital audio data is
converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The
bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue
audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock
jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion.
The analogue outputs from the DACs can then be mixed with other analogue inputs using the output
mixers LOMIX, ROMIX and the speaker output mixer SPKMIX.
The DACs are enabled by the DACL_ENA and DACR_ENA register bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
1
DACL_ENA
(rw)
0b
Left DAC Enable
0 = DAC disabled
1 = DAC enabled
R3 (03h)
0
DACR_ENA
(rw)
0b
Right DAC Enable
0 = DAC disabled
1 = DAC enabled
Table 16 DAC Enable Control
DAC DIGITAL VOLUME CONTROL
The output level of each DAC can be controlled digitally over a range from -71.625dB to 0dB in
0.375dB steps. The level of attenuation for an eight-bit code X is given by:
0.375
× (X-192) dB for 1 ≤ X ≤ 192;
MUTE for X = 0
0dB for 192
≤ X ≤ 255
The DAC_VU bit controls the loading of digital volume control data. When DAC_VU is set to 0, the
DACL_VOL or DACR_VOL control data will be loaded into the respective control register, but will not
actually change the digital gain setting. Both left and right gain settings are updated when a 1 is
written to DAC_VU. This makes it possible to update the gain of both channels simultaneously.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
R11 (0Bh)
7:0
DACL_VOL
[7:0]
1100_0000b
(0dB)
Left DAC Digital Volume
(See Table 18 for volume range)
8
DAC_VU
N/A
DAC Volume Update
Writing a 1 to this bit will cause left
and right DAC volume to be updated
simultaneously
R12 (0Ch)
7:0
DACR_VOL
[7:0]
1100_0000b
(0dB)
Right DAC Digital Volume
(See Table 18 for volume range)
Table 17 DAC Digital Volume Control



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