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WM8959 Datasheet(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8959 Datasheet(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 155 page  Pre-Production WM8959 w PP, May 2008, Rev 3.1 29 CONTROL INTERFACE TIMING – 2-WIRE MODE 2-wire mode is selected by connecting the MODE pin low. SDIN SCLK t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 Figure 7 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=HPVDD=SPKVDD=3.3V, DGND=AGND=HPGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK Frequency 526 kHz SCLK Low Pulse-Width t1 1.3 us SCLK High Pulse-Width t2 600 ns Hold Time (Start Condition) t3 600 ns Setup Time (Start Condition) t4 600 ns Data Setup Time t5 100 ns SDIN, SCLK Rise Time t6 300 ns SDIN, SCLK Fall Time t7 300 ns Setup Time (Stop Condition) t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed tps 0 5 ns |
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