 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
R5F564MFDDFB Datasheet(PDF) 102 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F564MFDDFB Datasheet(HTML) 102 Page - Renesas Technology Corp |
|
|
102 / 162 page  R01DS0173EJ0120 Rev.1.20 Page 102 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics 2.3.7.3 TMR Note 1. tPBcyc: PCLKB cycle Figure 2.36 TMR Clock Input Timing Table 2.27 TMR Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit*1 Test Conditions TMR Timer clock pulse width Single-edge setting tTMCWH, tTMCWL 1.5 — tPBcyc Figure 2.36 Both-edge setting 2.5 — PCLKB TMCI0 to TMCI3 tTMCWL tTMCWH |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
