R5F564MFDDFB datasheet(105/162 Pages) RENESAS

105 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 105 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.6

POE3

Note 1. tPBcyc: PCLKB cycle

Figure 2.40

POE# Input Timing

Figure 2.41

Output Disable Time for POE in Response to Transition of the POEn# Signal Level

Table 2.30

POE3 Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Typ.

Max.

Unit*1

Test Conditions

POE

POEn# input pulse width

tPOEW

1.5

—

tPBcyc

Figure 2.40

Output

isable time

Transition of the

POEn# signal

level

tPOEDI

—

5 PCLKB + 0.24

µs

Figure 2.41

When detecting falling edges

(ICSRm.POEnM[3:0] = 0000b

(m = 1 to 5, n = 0, 4, 8, 10, 11))

Simultaneous

conduction of

output pins

tPOEDO

—

3 PCLKB + 0.2

µs

Figure 2.42

tPOEDS

—

1 PCLKB + 0.2

µs

Figure 2.43

Time for access to the register is

not included.

Oscillation stop

detection

tPOEDOS

—

µs

Figure 2.44

POEn# input

PCLKB

tPOEW

POEn# input

(n = 0, 4, 8, 10, 11)

MTU PWM output pins

Outputs disabled

tPOEW

tPOEDI

R5F564MFDDFB Datasheet(PDF) 105 Page - Renesas Technology Corp

R5F564MFDDFB Datasheet(HTML) 105 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL