R5F564MFDDFB datasheet(107/162 Pages) RENESAS

107 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 107 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.7

GPT

Note 1. tPAcyc: PCLKA cycle

Figure 2.45

GPT Input Capture Input Timing

Figure 2.46

GPT External Trigger Input Timing

Table 2.31

GPT Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

GPT

Input capture input pulse

width

Single-edge

setting

tGTICW

3—

tPAcyc

Figure 2.45

Both-edge

setting

5—

External trigger input pulse

width

Single-edge

setting

tGTEW

1.5

—

tPAcyc

Figure 2.46

Both-edge

setting

2.5

—

Input capture

input

PCLKA

tGTICW

External trigger

PCLKA

tGTEW

R5F564MFDDFB Datasheet(PDF) 107 Page - Renesas Technology Corp

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