R5F564MFDDFB datasheet(109/162 Pages) RENESAS

109 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 109 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

Figure 2.47

SCK Clock Input Timing

Figure 2.48

SCI Input/Output Timing: Clock Synchronous Mode

Note:

tIICcyc: RIIC internal reference clock (IICφ) cycle

Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by

Table 2.33

Simple IIC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.*1, *2

Max.

Unit

Test

Conditions

Simple IIC

(Standard-mode)

SSDA input rise time

tSr

—

1000

Figure 2.49

SSDA input fall time

tSf

—

300

SSDA input spike pulse removal

time

tSP

04 × tPBcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

—

400

Simple IIC

(Fast-mode)

SSCL, SSDA input rise time

tSr

—

300

SSCL, SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse

removal time

tSP

04 × tPBcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

—

400

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 0 to 12)

tTXD

tRXS tRXH

TxDn

RxDn

SCKn

n = 0 to 12

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