R5F564MFDDFB datasheet(116/162 Pages) RENESAS

116 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 116 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.10

RSPI

Note 1. tPAcyc: PCLKA cycle

Note 2. We recommend that pins suffixed with the same letter such as -A and -B, indicating grouping of the pins, should be used as a

set. The AC characteristics of the RSPI are measured using the pins from the same group.

Table 2.36

RSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.*1

Max.*1

Unit*1

Test

Conditions*2

RSPI

RSPCK clock cycle

Master

tSPcyc

4096

tPAcyc

Figure 2.56

Slave

—

RSPCK clock high

pulse width

Master

tSPCKWH

(tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKR

– tSPCKF) / 2

—

RSPCK clock low

pulse width

Master

tSPCKWL

(tSPcyc – tSPCKR

– tSPCKF) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKR

– tSPCKF) / 2

—

RSPCK clock rise/

fall time

Output

tSPCKr,

tSPCKf

—5

Input

—

µs

Data input setup

time

Master

tSU

—

Figure 2.57 to

Figure 2.62

Slave

8.3 – tPAcyc

—

Data input hold

time

Master

PCLKA division

ratio set to 1/2

tHF

0—

PCLKA division

ratio set to a

value other than

1/2

tPAcyc

—

Slave

8.3 + 2 × tPAcyc

—

SSL setup time

Master

tLEAD

tSPcyc

Slave

—

tPAcyc

SSL hold time

Master

tLAG

tSPcyc

Slave

—

tPAcyc

Data output delay

time

Master

tOD

—6.3

Slave

—

3 × tPAcyc +

Data output hold

time

Master

tOH

0—

Slave

—

Successive

transmission delay

time

Master

tTD

tSPcyc + 2 × tPAcyc

8 × tSPcyc

+ 2 × tPAcyc

Slave

4 × tPAcyc

—

MOSI and MISO

rise/fall time

Output

tDr, tDf

—5

Input

—

µs

SSL rise/fall time

Output

tSSLr,

tSSLf

—5

Input

—

µs

Slave access time

tSA

—4

tPAcyc

Figure 2.61,

Figure 2.62

Slave output release time

tREL

—3

tPAcyc

R5F564MFDDFB Datasheet(PDF) 116 Page - Renesas Technology Corp

R5F564MFDDFB Datasheet(HTML) 116 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL