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R5F564MFDDFB Datasheet(PDF) 134 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 134 Page - Renesas Technology Corp |
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134 / 162 page ![]() R01DS0173EJ0120 Rev.1.20 Page 134 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics 2.3.7.18 CAC Note 1. tPBcyc: PCLKB cycle Note 2. tCAC: CAC count clock source cycle Table 2.44 CAC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item*1, *2 Symbol Min.*1 Max. Unit*1 Test Conditions CAC CACREF input pulse width tPBcyc ≤ tcac tCACREF 4.5 tcac + 3 tPBcyc —ns tPBcyc > tcac 5 tcac + 6.5 tPBcyc — |
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