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9DBL0853ANDGI Datasheet(PDF) 5 Page - Renesas Technology Corp |
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9DBL0853ANDGI Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 32 page ![]() 5 ©2020 Renesas Electronics Corporation December 9, 2022 9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet Pin Descriptions Table 1. Pin Descriptions Pin Name [a] [b] [c] Type Description 08x3 Pin No. 06x3 Pin No. 04x3 Pin No. 02x3 Pin No. ^CKPWRGD_PD# Input Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal 120k Ω pull-up resistor. 48 40 31 22 ^vHIBW_BYPM_LOBW# Latched In Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2 (Bypass mode) with internal pull-up/pull-down resistors. See ZDB Operating Mode for details. 2 2 1 24 CLK_IN Input True Input for differential reference clock. 6 6 5 4 CLK_IN# Input Complementary input for differential reference clock. 7 7 6 5 DIF0 Output Differential true clock output. 15 14 13 11 DIF0# Output Differential complementary clock output. 16 15 14 12 DIF1 Output Differential true clock output. 18 18 17 17 DIF1# Output Differential complementary clock output. 19 19 18 18 DIF2 Output Differential true clock output. 23 22 22 – DIF2# Output Differential complementary clock output. 24 23 23 – DIF3 Output Differential true clock output. 26 27 27 – DIF3# Output Differential complementary clock output. 27 28 28 – DIF4 Output Differential true clock output. 32 33 – – DIF4# Output Differential complementary clock output. 33 34 – – DIF5 Output Differential true clock output. 35 36 – – DIF5# Output Differential complementary clock output. 36 37 – – DIF6 Output Differential true clock output. 41 – – – DIF6# Output Differential complementary clock output. 42 – – – DIF7 Output Differential true clock output. 44 – – – DIF7# Output Differential complementary clock output. 45 – – – EPAD GND Connect to ground. 49 41 33 25 FB_DNC DNC True clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 3 3 2 1 FB_DNC# DNC Complement clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 4 4 3 2 GND GND Ground pin. 22 – – – GND GND Ground pin. 40 – – – GNDA GND Ground pin for the PLL core. 29 – – – GNDDIG GND Ground pin for digital circuitry. 9 8 8 6 |
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