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©2020 Renesas Electronics Corporation

December 9, 2022

9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet

Table 5. 12kHz to 20MHz Phase Jitter [a] [b]

[a] Guaranteed by design and characterization, not 100% tested in production.

[b] Additive jitter is calculated using Root-Sum-Square (RSS) subtraction.

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

tjph156M12k-20

Additive Phase Jitter,

Fanout Mode

156.25MHz, 12kHz to 20MHz.

–

363

–

fs

(rms)

Table 6. Clock Input Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

VCROSS

Input Crossover Voltage [a]

[a] Guaranteed by design and characterization, not 100% tested in production.

Crossover voltage.

150

–

900

mV

VSWING

Input Swing [a]

Differential value.

300

–

mV

dv/dt

Input Slew Rate [a] [b]

[b] Slew rate measured through ±75mV window centered around differential zero.

Measured differentially.

0.4

–

8

V/ns

IIN

Input Leakage Current

VIN = VDD , VIN = GND.

-5

–

5

μA

dtin

Input Duty Cycle [a]

Differential measurement.

45

–

55

%

JDIFIn

Input Jitter – Cycle to Cycle [a]

0

–

125

ps

Table 7. Output Duty Cycle, Skew and PLL Characteristics [a]

[a] Guaranteed by design and characterization, not 100% tested in production.

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

BW

PLL BW [b]

[b] The Minimum/Typical/Maximum values of each BW setting track each other, i.e., maximum low BW will never occur with minimum high BW.

-3dB point in High BW Mode (100MHz).

2

3.3

4

MHz

-3dB point in Low BW Mode (100MHz).

1

1.5

2

MHz

tJPEAK

PLL Jitter Peaking

Peak Pass band gain (100MHz).

0.8

2

dB

tDC

Duty Cycle [c]

[c] Measured from differential waveform.

Measured differentially, PLL Mode.

45

50

55

%

tDCD

Duty Cycle Distortion [c] [d]

[d] Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

Measured differentially, Bypass Mode.

-1

0.0

1

%

tpdBYP

Skew, Input to Output [e]

[e] All outputs at default slew rate.

Bypass Mode, VT = 50%.

2500

3440

4500

ps

tpdPLL

PLL Mode VT = 50%.

-100

8

100

ps

tsk3

Skew, Output to Output [e]

VT = 50%.

22

50

ps

tjcyc-cyc

Jitter, Cycle to Cycle

PLL Mode.

15

50

ps