9DBL0853ANDGI datasheet(14/32 Pages) RENESAS

14 / 32 page

December 9, 2022

9DBL02x3/9DBL04x3/ 9DBL06x3/9DBL08x3 Datasheet

Power Management

ZDB Operating Mode

Table 14. SMBus Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

VILSMB

SMBus Input Low Voltage

VDDSMB = 3.3V.

0.8

VIHSMB

SMBus Input High Voltage

VDDSMB = 3.3V.

2.1

3.6

VOLSMB

SMBus Output Low Voltage

At IPULLUP.

0.4

IPULLUP

SMBus Sink Current

At VOL.

VDDSMB

Nominal Bus Voltage

2.7

3.6

tRSMB

SCLK/SDATA Rise Time [a]

[a] Guaranteed by design and characterization, not 100% tested in production.

(Max VIL - 0.15) to (Min VIH + 0.15).

1000

tFSMB

SCLK/SDATA Fall Time [a]

(Min VIH + 0.15) to (Max VIL - 0.15).

300

fSMB

SMBus Operating Frequency [b] [c]

[b] The device must be powered up for the SMBus to function.

[c] The differential input clock must be running for the SMBus to be active.

SMBus operating frequency.

500

kHz

Table 15. LOS Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum Units

tLOS

CLK-IN Loss of Signal Detect Time

–

4.2

tLOSREL

CLK-IN Loss of Signal Release Time

–

0.12

0.5

Table 16. Power Management

CKPWRGD_PD#

CLK_IN

SMBus OEn bit

OEn# Pin

DIFn

DIFn#

PLL State

(ZDB Mode)

Low [a]

[a] The output state is set by B11[1:0] (Low/Low default)

Low [a]

Off

Running

Low [a]

On [b]

[b] If Bypass mode is selected, the PLL will always be off.

Running

On [b]

Running

Low [a]

On [b]

Table 17. ZDB (PLL) Operating Mode[a]

[a] ‘10’ value is reserved.

HiBW_BypM_LoBW#

Operating Mode

Byte1 [7:6] Readback

Byte1 [4:3] Control

Low Bandwidth PLL (ZDB) Mode

Mid-level (VDD/2)

Bypass Mode (Fanout buffer)

High Bandwidth PLL (ZDB) Mode

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